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Cypress CY7C1246V18, CY7C1248V18, CY7C1250V18, CY7C1257V18 Switching Waveforms

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CY7C1246V18, CY7C1257V18

CY7C1248V18, CY7C1250V18

Document Number: 001-06348 Rev. *D Page 23 of 27

Switching Waveforms

Read/Write/Deselect Sequence[28, 29, 30]

Figure 5. Waveform for 2.0 Cycle Read Latency

DON’T CARE UNDEFINED

12345678910

READ READ

READ NOP WRITE

WRITE

NOP

11

R/W

tKH tKL tCYC

tHC

tSA tHA

A0 A1 A2 A3 A4

QVLD

NOP

QVLD

tCCQO

tCQOH

QVLD

NOP

KHKH

(Read Latency = 2.0 Cycles)

NOP NOP

CCQO

tSD

tHD

tCLZ tCHZ

D20 D21 D30 D31

CQDOH

Q00 Q11

Q01 Q10

tDOH

tCO

Q40 Q41

tCQD

tCQH

CQHCQH

Notes

28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

29.Outputs are disabled (High-Z) one clock cycle after a NOP.

30.The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency

operation, it may be required to avoid bus contention.

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Contents

Main CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Functional Description Selection Guide CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1246V18) Logic Block Diagram (CY7C1257V18) 2M x 8 Array 2M x 8 Array Logic Block Diagram (CY7C1248V18) Logic Block Diagram (CY7C1250V18) 1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations CY7C1246V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1257V18 (4M x 9) CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations CY7C1248V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1250V18 (1M x 36) CY7C1246V18, CY7C1257V18 Pin Definitions CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Definitions CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Page Page CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Page TAP Controller State Diagram TAP Controller Block Diagram TAP Controller TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document Number: 001-06348 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence READ NOP WRITE READ READ 12345678910 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Ordering Information CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Ordering Information Document Number: 001-06348 Rev. *D Page 26 of 27 Package Diagram [+] Feedback [+] Feedback Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 51-85195-*A Document History Page