Cypress CY7C1246V18, CY7C1248V18, CY7C1250V18, CY7C1257V18 Logic Block Diagram (CY7C1248V18), Logic Block Diagram (CY7C1250V18)

CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
Document Number: 001-06348 Rev. *D Page 3 of 27
Logic Block Diagram (CY7C1248V18)
Logic Block Diagram (CY7C1250V18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W DQ[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS[1:0]
VREF
Write Add. Decode
18 18
LD
Control
20
1M x 18 Array
1M x 18 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W DQ[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS[3:0]
VREF
Write Add. Decode
36 36
LD
Control
19
512K x 36 Array
512K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
36
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