![This problem may affect UART, IrDA, and FSK implementations.](/images/new-backgrounds/129514/1295143x1.webp)
CY8CTST120, CY8CTMG120, CY8CTMA120
1.Internal Main Oscillator (IMO) tolerance deviation at temperature extremes.
PROBLEM DEFINITION
Asynchronous digital communication interfaces may fail framing beyond 0 to 70°C. This problem does not affect end product usage between 0 and 70°C.
PARAMETERS AFFECTED
The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and within the upper and lower data sheet temperature range is ±5%.
TRIGGER CONDITION
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±4% when operated beyond the temperature range of 0 to +70°C.
SCOPE OF IMPACT
This problem may affect UART, IrDA, and FSK implementations.
WORKAROUND
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
FIX STATUS
The cause of this problem and its solution has been identified. Silicon fix is planned to correct the deficiency in silicon.
2.The DP line of the USB interface may pulse low when the PSoC® device wakes from sleep causing an unexpected wakeup of the host computer
PROBLEM DEFINITION
When the device is operating at 4.75V to 5.25V and the 3.3V regulator is enabled, a short low pulse may be created on the DP signal line during device wakeup. The 15 µs to 20 µs low pulse of the DP line may be interpreted by the host computer as a
PARAMETERS AFFECTED
The bandgap reference voltage used by the 3.3V regulator decreases during sleep due to leakage. Upon device wakeup, the bandgap is
WORKAROUND
To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient method is to set the No Buzz bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered and output stable during sleep. Setting the No Buzz bit results in a nominal 100 µA increase to sleep current. Leaving the analog reference block enabled during sleep also resolves this issue because it forces the bandgap to remain enabled. An example to disable the No Buzz bit is as follows.
Assembly
M8C_SetBank1
or reg[OSC_CR0], 0x20 M8C_SetBank0
C
OSC_CR0 = 0x20;
September 25, 2008 | Document No. | 2 |
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