CY8CTST120, CY8CTMG120, CY8CTMA120
and A, 0xf8 ;clear the clock bits (briefly chg the cpu_clk to 3Mhz) or A, 0x02 ;will set clk to 12Mhz
mov reg[OSC_CR0],A ;clk is now set at 12Mhz M8C_SetBank0
.loop:
mov A, reg[PMA0_DR] ; Get the data from the PMA space mov [X], A ; save it in data array
inc X ; increment the pointer
dec [USB_APITemp+1] ; decrement the counter jnz .loop ; wait for count to zero out
;;
;;24Mhz read PMA workaround (back to previous clock speed)
pop A ;recover previous reg[OSC_CR0] value M8C_SetBank1
mov reg[OSC_CR0],A ;clk is now set at previous value M8C_SetBank0
;;end 24Mhz read PMA workaround
References
[1]Document #
[2]Document #
[3]Document #
September 25, 2008 | Document No. | 4 |
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