Dell R910 manual PowerEdge R810 and M910, FlexMem Bridge Technology

PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance

bin SKUs)	(Slower with QR DIMMs)
Minimum memory population	1 DIMM	2 DIMMs
		(must populate with identical
		DIMM pairs)
Hemisphere Mode	No	Yes
Memory RAS Features	ECC, DIMM Sparing, Lock-step,	Enhanced ECC, DIMM sparing,
	Mirroring, x4 or x8 SDDC	Lock-step, Mirroring, x4 or x8
		SDDC, Rank sparing

PowerEdge R810 and M910

The R810 and M910 servers utilize DDR3 memory providing a high performance, high-speed memory interface capable of low latency response and high throughput. The R810 and M910 support Registered DDR3 DIMMs (RDIMMs) only.

The R810 and M910 utilize Intel Xeon 7500 and 6500 series processors that have four SMI channels for each socket. Each of those memory controllers then has two SMI channels that connect to the Intel 7500 Scalable Memory Buffer.

The DDR3 memory interface consists of eight Intel 7500 Scalable Memory Buffers (two per socket), each of which has two DDR3 memory channels. Each channel supports up to two RDIMMs for single/dual/quad rank. By limiting to two DIMMs per DDR channel, the system can support quad-rank DIMMs at 1066 MTs. The R810 and M910 support a maximum of 32 DIMMS with four SMI channels per socket, two Intel 7500 Scalable Memory Buffers per SMI channel, and two DDR3 channels per memory buffer supporting two DIMMs each.

FlexMem Bridge Technology

In a four-CPU configuration, the R810 and M910 use only one memory controller per CPU. This single controller connects to two memory buffers via SMI links. Each memory buffer in turn connects to four DDR3 DIMMs with a total of 32 DIMMs accessible. In a two-CPU configuration, normally this would mean that only four memory buffers are connected; therefore, a total of only 16 DIMMs are accessible.

To overcome this limitation with two CPUs, the R810 and M910 use a pass-through, called the FlexMem Bridge, in the sockets without CPUs (CPU 3 and CPU 4). This allows CPU 1 and CPU 2 to connect to the memory of their respective adjacent sockets (CPU 3 and CPU 4) and access the additional 16 DIMMs.

The FlexMem Bridge provides the following:

•Two pass-through links for SMI

•One pass-through link for QPI

•The pass-through SMI links connect the two installed CPUs to additional Intel 7500 Scalable Memory Buffers; therefore, the CPUs will have the following memory attached:

•CPU 1 will have access to DIMMs A1-A8 and to DIMMs C1-C8 (those normally associated with CPU 3)

•CPU 2 will have access to DIMMs B1-B8 and to DIMMs D1-D8 (those normally associated with CPU 4)

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