Dell R910, M910, R810 manual Introduction, Quick Reference Guide Terminology Definitions

PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance

Introduction

This paper serves as memory guidance for Dell™ 11th Generation PowerEdge™ R810, R910, and M910 servers released March 2010 using the new Intel® Xeon® 7500 and 6500 series processors that support DDR3 memory technology. This document explains what Dell supports and describes rules for installing memory. Examples of terminology definitions and details about performance or Reliability, Availability, and Serviceability (RAS) features are shown as follows.

Quick Reference Guide (Terminology Definitions)

DDR3 (Double Data Rate): The latest (3rd) generation of DDR DRAM; replaces DDR and DDR2 memory.

DIMM: Dual Inline Memory Module. This is the memory stick that is installed in each memory slot. It is comprised of multiple memory chips and, in some cases, registers, buffers and/or temperature sensors.

Dual Rank (DR): Two rows of DRAM comprising 64 bits of data each.

ECC (Error Checking and Correcting): This memory coding method is able to correct and identify certain types of DRAM and interface errors.

Enhanced ECC: Like ECC, but this memory coding method protects against additional memory error types including control line errors.

Hemisphere Mode: This mode allows interleaving between a processor’s two memory controllers leading to improved performance. Interleaving also adds benefits to memory thermal performance by spreading memory accesses across multiple DIMMs and reducing memory “hot spots.”

Lock-step:Pairs of DIMMs are accessed as a single double-wide (128-data bit) DIMM, allowing more powerful error-correction codes to be used, including detecting address errors.

MC: Memory Controller

Intel 7500 Scalable Memory Buffer: Translates one Scalable Memory Interconnect (SMI) bus into two DDR3 buses. Intel Xeon 7500 and 6500 series processors must have this device to operate.

Mirror Mode (Mirroring): Two memory controllers are configured to allow the same data to be written to each. Each controller’s data is identical to the other; thus, if one fails or has multiple bit errors, there is a backup. The operating system will report half of your installed memory.

Quad Rank (QR): Four rows of DRAM comprising 64 bits of data each.

Rank: A row of DRAM devices comprising 64 bits of data per DIMM.

RAS: Reliability, Availability, and Serviceability

SDDC: Single Device Data Correction. Memory systems that utilize Single Device Data Correction can detect and correct multiple bit errors that come from a single memory chip on the DIMM.

Single Rank (SR): One row of DRAM comprising 64 bits of data.

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