Emerson MVME3100 - page 24

Hardware Preparation and Installation

MVME3100 Single Board Computer Installation and Use (6806800M28C)

24

The MVME3100 is factory tested and shipped with the configuration described in the following

sections.

Contents

Main Trademarks Notice Limited and Restricted Rights Legend Contact Address Contents Page Page Page Page Page List of Tables List of Tables List of Figures Page About this Manual Overview of Contents As of the printing date of this manual, the MVME3100 supports the models listed below. Abbreviations This document uses the following abbreviations: Page Page Conventions The following table describes the conventions used throughout this manual. Page Summary of Changes Page Chapter 1 Hardware Preparation and Installation 1.1 Overview 1.2 Getting Started 1.2.1 Overview of Startup Procedures 1.2.2 Unpacking Guidelines 1.3 Declaration of Conformity 1.4 Configuring Hardware 1.4.1 MVME3100 Layout Page MVME3100 Single Board Computer Installation and Use (6806800M28C) 25 Figure 1-1 Board Layout 1.4.2 Configuration Switch (S4) 1.4.3 Geographical Address Switch (S3) Table 1-2 Configuration Switch (S4) Settings (continued) Figure 1-2 Geographical Address Switch Settings Table 1-3 Geographical Address Switch Assignments Note: 1SW2 has been configured to work in PCI-X mode only. The default setting is OFF. Table 1-3 Geographical Address Switch Assignments (continued) Table 1-4 Slot Geographical Address Settings 1.4.4 PMC I/O Voltage Configuration 1.4.5 RTM SEEPROM Address Switch (S1) 1.5 Installing Hardware 1.6 Connecting to Peripherals Page 1.7 Completing the Installation Page Chapter 2 Startup and Operation 2.1 Introduction 2.2 Applying Power 2.3 Switches and Indica tors Page Page Startup and Operation Table 2-3 Additional Onboard Status Indicators Startup and Operation Table 2-3 Additional Onboard Status Indicators (continued) Page Chapter 3 MOTLoad Firmware 3.1 Overview 3.2 Implementation and Memory Requirements 3.3 MOTLoad Commands 3.3.1 Utilities 3.3.2 Tests 3.3.3 Command List Page Page Page Page 3.4 Using the Command Line Interface Page 3.4.1 Command Line Rules 3.4.2 Command Line Help 3.5 Firmware Settings 3.5.1 Default VME Settings Page Page Page 3.5.2 Control Register/Control Status Register Settings 3.5.3 Displaying VME Settings 3.5.4 Editing VME Settings 3.5.5 Deleting VME Settings 3.5.6 Restoring Default VME Settings 3.6 Remote Start 3.7 Alternate Boot Images and Safe Start 3.8 Firmware Startup Sequence Following Reset 3.9 Firmware Scan for Boot Image Page 3.10 Boot Images 3.10.1 Checksum Algorithm 3.10.2 Image Flags 3.10.3 User Images 3.10.4 Alternate Boot Data Structure 3.10.5 Alternate Boot Images and Safe Start 3.10.6 Boot Image Firmware Scan 3.11 Startup Sequence Page Chapter 4 Functional Description 4.1 Overview 4.2 Features Table 4-1 MVME3100 Features Summary (continued) Table 4-2 MVME721 RTM Features Summary Table 4-1 MVME3100 Features Summary (continued) Page Page MVME3100 Single Board Computer Installation and Use (6806800M28C) 74 4.4 Processor P2 4.5 System Memory Figure 4-2 MVME721 RTM Block Diagram Rear Panel 4.6 Local Bus Interface 4.6.1 Flash Memory 4.6.2 Control and Timers Logic 4.7 I2C Serial Interface and Devices 4.8 Ethernet Interfaces 4.9 Asynchronous Serial Ports 4.10 PCI/PCI-X Interfaces and Devices 4.10.1 MPC8540 PCI-X Interface 4.10.2 TSi148 VME Controller 4.10.3 Serial ATA Host Controller 4.10.4 PCI-X-to-PCI-X Bridges 4.10.5 PCI Mezzanine Card Slots 4.10.6 USB 4.10.7 PMC Expansion 4.11 General-Purpose Timers 4.12 Real-time Clock Battery 4.13 Reset Control Logic Page Chapter 5 Pin Assignments 5.1 Overview 5.2 Connectors 5.2.1 PMC Expansion Connector (J4) Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) All PMC expansion signals are shared with the USB controller. Table 5-1 PMC Expansion Connector (J4) Pin Assignments (continued) 5.2.2 Ethernet Connectors (GENET1/J41B, GENET2/J2B, ENET1/J2A) 5.2.3 PCI Mezzanine Card (PMC) Connectors (J11 J14, J21 J23) Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments (continued) Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments Table 5-3 PMC Slot 1 Connector (J11) Pin Assignments (continued) Table 5-5 PMC Slot 1 Connector (J13) Pin Assignments Table 5-4 PMC Slot 1 Connector (J12) Pin Assignments (continued) Table 5-6 PMC Slot 1 Connector (J14) Pin Assignments Table 5-5 PMC Slot 1 Connector (J13) Pin Assignments (continued) Table 5-6 PMC Slot 1 Connector (J14) Pin Assignments (continued) Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments Table 5-8 PMC Slot 2 Connector (J22) Pin Assignments Table 5-7 PMC Slot 2 Connector (J21) Pin Assignments (continued) Table 5-9 PMC Slot 2 Connector (J23) Pin Assignments Table 5-8 PMC Slot 2 Connector (J22) Pin Assignments (continued) Table 5-9 PMC Slot 2 Connector (J23) Pin Assignments (continued) 5.2.4 Serial Port Connectors (COM1/J41A, COM2COM5/J2A-D) 5.2.5 VMEbus P1 Connector Table 5-11 VMEbus P1 Connector Pin Assignments (continued) 5.2.6 VMEbus P2 Connector 5.2.7 MVME721 PMC I/O Module (PIM) Connectors (J10, J14) Table 5-13 MVME721 Host I/O Connector (J10) Pin Assignments (continued) 5.2.8 Planar sATA Power Connector (J30) 5.2.9 USB Connector (J27) 5.2.10 sATA Connectors (J28 and J29) 5.3 Headers 5.3.1 Boundary Scan Header (J24) 5.3.2 Processor COP Header (J25) Chapter 6 Memory Maps 6.1 Memory Maps 6.1.1 Default Processor Memory Map 6.1.2 MOTLoads Processor Memory Map 6.1.3 VME Memory Map 6.1.4 System I/O Memory Map 1. Reserved for future implementation 2. 32-bit write only 3. Byte read/write capable Table 6-3 System I/O Memory Map (continued) 6.1.5 System Status Register 6.1.6 System Control Register 6.1.7 System Indicator Register 6.1.8 Flash Control/Status Register 6.1.9 PCI Bus Status Registers Page Page 6.1.10 Interrupt Detect Register 6.1.11 Presence Detect Register 6.1.12 PLD Revision Register 6.1.13 PLD Data Code Register 6.1.14 Test Register 1 6.1.15 Test Register 2 6.1.16 External Timer Registers 6.1.16.1 Prescalar Register 6.1.16.2 Control Registers 6.1.16.3 Compare Registers 6.1.16.4 Counter Registers 6.1.17 Geographical Address Register Chapter 7 Programming Details 7.1 Introduction 7.2 MPC8540 Reset Configuration Page Page Page Page 7.3 MPC8540 Interrupt Controller 7.4 Local Bus Controller Chip Select Assignments 7.5 Two-Wire Serial Interface 7.6 User Configuration EEPROM Table 7-4 I2C Bus Device Addressing (continued) 7.7 VPD EEPROM 7.8 RTM VPD EEPROM 7.9 Ethernet PHY Address 7.10 Flash Memory 7.11 PCI IDSEL Definition Table 7-7 IDSEL and Interrupt Mapping for PCI Devices (continued) Table 7-8 Planar PCI Device Identification 7.12 PCI Arbitration Assignments 7.13 Clock Distribution Page 7.14 MPC8540 Real-Time Clock Input 7.15 MPC8540 LBC Clock Divisor Appendix A A.1 Power Requirements A.2 Environmental Specifications Specifications A.3 Thermally Significant Components Page Page Appendix B B.1 Emerson Network Power - Embedded Computing Documents B.2 Manufacturers Documents Table B-2 Manufacturers Documents (continued) B.3 Related Specifications Table B-2 Manufacturers Documents (continued) Table B-3 Related Specifications Table B-3 Related Specifications (continued) Page Safety Notes EMC Safety Notes Installation Configuration Switches/Jumpers Page Page Sicherheitshinweise Sicherheitshinweise EMV Installation Sicherheitshinweise Schaltereinstellungen Betrieb Umweltschutz Page HOW TO REACH LITERATURE AND TECHNICAL SUPPORT: