PSB No.: S-0062I

Page: 1 of 18

ENDEAVOR WG / PROGRESSION 4

VER

PART #

DESC

TYPE

LOC

REASON

1.04.1.08

 

SYSTEM

27C010

U1

INITIAL RELEASE

1.04.1.08

 

SETUP

27C512

U113

 

1.06.1.09

2013112

SYSTEM

27C010

U1

Three text modes 62h,64h and 65h

1.06.1.09

2013113

SETUP

27C512

U113

have been restored. Incorporated new

 

 

 

 

 

VGA BIOS (v1.10.03) which changed

 

 

 

 

 

mode 072h (1024X768X4) back to

 

 

 

 

 

interlaced. Fixed problem between

 

 

 

 

 

EMM386.EXE and User defined HDD

 

 

 

 

 

parameter tables from the BIOS

 

 

 

 

 

extended data area into the shadow

 

 

 

 

 

RAM. Fixes problem where User

 

 

 

 

 

Defined HDD table different from pre-

 

 

 

 

 

defined HDD for the same drive by one

 

 

 

 

 

cylinder. Fixed problem in pre-defined

 

 

 

 

 

HDD tables where control byte was not

 

 

 

 

 

properly set for some drives with more

 

 

 

 

 

than 8 heads. Added WD1170 HDD in

 

 

 

 

 

the pre-defined HDD table as type 30.

 

 

 

 

 

(SEE ECN NO: ENDVWG-001)

 

 

 

 

 

08/06/93.

1.13.1.14

201311201

SYSTEM

27C010

U1

Corrected jagged cursor display in

1.13.1.14

201311301

SETUP

27C512

U113

interlaced mode with the BT-482

 

 

 

 

 

RAMDAC when using the hardware

 

 

 

 

 

cursor Wingine display drivers. Serial

 

 

 

 

 

BIOS has been expanded to support

 

 

 

 

 

COM3 and COM4. Parallel BIOS has

 

 

 

 

 

been corrected to provide support for

 

 

 

 

 

LPT1-LPT3. Corrected inability to run

 

 

 

 

 

SETUP when an adaptec AHA-1540C

 

 

 

 

 

or 1542C SCSI host adapter is installed

 

 

 

 

 

by modifying POD to run external ROM

 

 

 

 

 

initialization routines just prior to

 

 

 

 

 

invocation of SETUP. Corrected

 

 

 

 

 

timing of parallel port STROBE signal

 

 

 

 

 

to allow for slow rise time and longer

 

 

 

 

 

cable lengths. Removed internal

 

 

 

 

 

cache test. The cache test failed,

 

 

 

 

 

regardless of cache condition. Since

 

 

 

 

 

the 80486 CPU perform internal cache

 

 

 

 

 

testing at power-up, disabling the POD

 

 

 

 

 

cache test will not affect system

 

 

 

 

 

performance. (SEE ECN NO: PROG4-

 

 

 

 

 

002) 12/03/93.