+0 / − 7.8ms

RTC - 4543 SA/SB

7-3. Data writes (Divider Reset)

CE

 

 

 

 

 

 

 

 

 

 

 

 

WR

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

 

 

 

 

 

 

 

 

 

52

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N Seconds

 

 

 

 

 

 

DATA

s1

s2

s4

s8

s10

s20

s40

y8

y10

y20

y40

y80

Timer,counter

N seconds

 

 

 

 

0 seconds

 

 

 

 

N seconds

Divider reset

Pulse

Carry stop

Pulse

After the counter is reset, carries to the seconds digit are halted.After the data write operation, the prohibition on carries to the seconds counter is lifted by setting the CE pin low.

Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier.

7-4. FOUT output and 1 Hz carries

CE

WR

tCES

CLK

1Hz

FOUT

1.0s -7.80ms

tCLK

15.6 ms

15.6 ms

During a data write operation, because a reset is applied to the Devider counter (from the 128 Hz level to the 1 Hz level) after the CE pin goes high during the time between the falling edge of the first clock cycle and the rising edge of the second clock cycle, the length of the first 1 Hz cycle after the

data write operation is 1.0 s +tCES+tCLK. Subsequent cycles are output at 1.0-second intervals. The 1-Hz signal that is output on FOUT is the internal 1-Hz signal with a 15.6-ms shift applied.

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