Freescale Semiconductor DSP56364

Features

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2

1-2 Freescale Semiconductor

Figure 1-1 DSP56364 Block Diagram

1.2 Features

• DSP56300 modular chassis

— 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V.

— Object Code Compatible with the 56K core.

— Data ALU with a 24 × 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit

arithmetic support.

— Program Control with position independent code support and instruction cache support.

— Six-channel DMA controller.

— PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider

factors (1 to 16) and power saving clock divider (2i: i = 0 to 7). Reduces clock noise.

— Internal address tracing support and OnCE‰ for Hardware/Software debugging.

— JTAG port.

CLOCK

GEN

INTERNAL

DATA BUS

SWITCH

EXTAL

PROGRAM

RAM

0.5K x 24

PROG R A M R O M

8K x 24

Bootstrap ROM

192 x 24

PROGRAM

INTERRUPT

CONT

PROGRAM

DECODE

CONT

PROGRAM

ADDRESS

GEN

YAB

XAB

PAB

YDB

XDB

PDB

GDB

MODA/IRQA

MODB/IRQB

DATA ALU

24 X 24+

56→

56-BIT MAC

TWO 56-BIT ACCUMULATORS

BARREL SHIFTER

MODD/IRQD

PLL

ADDRESS

GENERATION UNIT

OnCE™

DSP56300

GPIO ESAI

24-BIT

MEMORY

RAM

1K X 24

Y MEMORY

RAM

1.5K X 24

DDB

DAB

SIX CHANNELS

DMA UNIT

CORE

YM_EB

XM_EB

PM_EB

PIO_EB

24 BITS BUS

SHI

JTAG

RESET

POWER

MGMT

PINIT/NMI

DRAM & SRAM

BUS

INTERFACE

EXTERNAL

ADDRESS BUS

SWITCH

EXTERNAL

DATA BUS

SWITCH

ADDRESS

DATA

CONTROL

PERIPHERAL

EXPANSION

AREA

MEMORY

EXPANSION

AREA