Freescale Semiconductor DSP56364 - page 25

DSP56300 Core Functional Blocks
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 1-7
• Y memory expansion bus (YM_EB) to Y memory
• Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and PCU as well
as the memory-mapped registers in the peripherals
• DMA data bus (DDB) for carrying DMA data between memories and/or peripherals
• DMA address bus (DAB) for carrying DMA addresses to memories and peripherals
• Program Data Bus (PDB) for carrying program data throughout the core
• X memory Data Bus (XDB) for carrying X data throughout the core
• Y memory Data Bus (YDB) for carrying Y data throughout the core
• Program address bus (PAB) for carrying program memory addresses throughout the core
• X memory address bus (XAB) for carrying X memory addresses throughout the core
• Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1, DSP56364 block
diagram.
1.5.5 Direct Memory Access (DMA)
The DMA block has the following features:
• Six DMA channels supporting internal and external accesses
• One-, two-, and three-dimensional transfers (including circular buffering)
• End-of-block-transfer interrupts
• Triggering from interrupt lines and all peripherals
1.5.6 PLL-based Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN),
which performs low-power division and clock pulse generation. PLL-based clocking:
• Allows change of low-power divide factor (DF) without loss of lock
• Provides output clock with skew elimination
• Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16), and a
power-saving clock divider (2i: i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input. This feature offers two immediate benefits:
• A lower frequency clock input reduces the overall electromagnetic interference generated by a
system.
• The ability to oscillate at different frequencies reduces costs by eliminating the need to add
additional oscillators to a system.