Internal I/O Memory Map
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor 1-9
memory switch can be accomplished provided that the affected address ranges are not being accessed
during the instruction cycle in which the switch operation takes place. Accordingly, the following
condition must be observed for trouble-free dynamic switching:
NOTE
No accesses (including instruction fetches) to or from the affected address
ranges in program and data memories are allowed during the switch cycle.
NOTE
The switch cycle actually occurs 3 instruction cycles after the instruction
that modifies the MS bit.
Any sequence that complies with the switch condition is valid. For example, if the program flow executes
in the address range that is not affected by the switch, the switch condition can be met very easily. In this
case a switch can be accomplished by just changing the MS bit in OMR in the regular program flow,
assuming no accesses to the affected address ranges of the data memory occur up to 3 instructions after the
instruction that changes the OMR bit. Special care should be taken in relation to the interrupt vector
routines since an interrupt could cause the DSP to fetch instructions out of sequence and might violate the
switch condition.
Special attention should be given when running a memory switch routine using the OnCE™ port. Running
the switch routine in Trace mode, for example, can cause the switch to complete after the MS bit change
while the DSP is in Debug mode. As a result, subsequent instructions might be fetched according to the
new memory configuration (after the switch), and thus might execute improperly.
1.6.5 External Memory Support
The DSP56364 does not support the SSRAM memory type. It does support SRAM and DRAM as
indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM. Note that the DSP56364 has only an 8-bit data bus. This means that no instruction fetches
from external memory are possible, and care should be taken to ensure that no program memory instruction
fetch access occurs in the external memory space. The DMA may be used to automatically pack and
unpack 24-bit data into the 8-bit wide external memory, during DMA data transfers.
Also, care should be taken when accessing external memory to ensure that the necessary address lines are
available. For example, when using glueless SRAM interfacing, it is possible to directly address 219
memory locations (512K) when using the 18 address lines and the two programmable address attribute
lines. Using DRAM access mode, the full 16M addressing range may be used.
1.7 Internal I/O Memory Map
The DSP56364 on-chip peripheral modules have their register files programmed to the addresses in the
internal X-I/O memory range (the top 128 locations of the X data memory space). See Section 3, “Memory
Configuration.”