General Interrupt Status Register
This register is at Base + 08H. Bit 0 is set when the first stage of
Bit 0 = 0 – No Interrupt
Bit 1 = 1 – Interrupt Active
NOTE: This bit is not set in
Reload Register
This register is at Base + 0CH. Write 1 to bit 8 will reload the
1.Write 80H to offset BAR + 0CH
2.Write 86H to offset BAR + 0CH
3.Write a ‘1’ to RELOAD[8] of the reload register
Offset 60 – 61H: WDT Configuration Register
Bit 5 indicates whether or not the WDT will toggle the WDT_TOUT# pin when WDT times out. (0 = Enabled, 1 = Disabled)
Bit 2 provides two options for prescaling the main
Bit [1:0] allows the user to choose the type of interrupt desired when the WDT reached the end of the first stage without being reset. (00 = IRQ, 01 = reserved, 10 = SMI, 11 = Disabled)
NOTE: The WDT does not support SMI now. IRQ uses APIC 1, INT 10 and it is active low, level triggered.
Offset 68H: WDT Lock Register
Bit 2 is used to choose the functionality of the timer. (0 = Watchdog Timer mode, 1 = Free running mode) The
Bit 1 enables or disables the WDT. (0 = Disabled, 1 = Enabled)
Bit 0 will lock the values of this register until a hard reset occurs or power is cycled. (0 = unlocked, 1 = locked) The default is Unlocked.
Watchdog Timer • 37