Intel® Solid-State Drive 530 Series (2.5-inch)
October 2013 Product Specification
Order Number: 329212-003US 15
4.2.2 Power Pin Signal Definitions
Table 12: Serial ATA Power Pin Definitions
Pin1 Name Definition Mating Order
P12 V33 3.3 V Power; not used 2nd Mate
P22 V33 3.3 V Power; not used 2nd Mate
P32 DevSleep Device Sleep Pin 1st Mate
P43,4 Ground 1st Mate
P53 Ground 1st Mate
P63 Ground 1st Mate
P73,5 V5 5 V Power 1st Mate
P83,5 V5 5 V Power 2nd Mate
P93,5 V5 5 V Power 2nd Mate
P103 Ground 1st Mate
P116 DAS Device Activity S ignal 2nd Mate
P123, 4 Ground 1st Mate
P132 V12 12 V Power; not used 1st Mate
P142 V12 12 V Power; not used 2nd Mate
P152 V12 12 V Power; not used 2nd Mate
Notes:
1. All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.
2. Pins P1, P2 and P3 are connected together; Pins P13, P14 and P15 are connected together. Although they are not
connected internally to the device, the host may apply voltage on these pins.
3. The mating sequence is:
• Ground pins P4-P6, P10, P12 and the 5 V power pin P7.
• Signal pins and the rest of the 5 V power pins P8-P9.
4. Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to
discharge ESD in a suitably config ured backplane connector.
5. Power pins P7, P8, and P9 are internally connected to one another within the device.
6. The host may ground P11 if it is not used for Device Activity Signal (DAS).
4.3 Device Sleep Feature