THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M1_DDR_A5
M0_DDR_DQ10
M0_DDR_CASN
M1_DDR_DM1
M1_DDR_WEN
C535 0.1uF
M1_DDR_DQ30
M0_DDR_DQ14
M0_DDR_VREFDQ
M1_DDR_DQ19
M1_DDR_DQS_N1
M1_DDR_DQS0
M1_DDR_A13
M0_DDR_DQ25
M1_DDR_RESET_N
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ4
M0_DDR_DQ4
M0_DDR_ODT
M0_DDR_DQ11
M0_DDR_DQ26
C561 0.1uF
M1_DDR_CKE
M1_DDR_A6
M0_DDR_A4
VDDC15_M1
M0_DDR_DQ10
M0_DDR_A3
M1_DDR_DQ18
M1_DDR_RASN
M1_DDR_DQ20
R544
240
1%
M0_DDR_RESET_N
M0_DDR_DQS2
M1_DDR_DQ7
M0_DDR_DQ26
M0_DDR_DQ25
R513
1K 1%
M1_DDR_DQ3
M0_DDR_A6
C501
0.1uF
M0_DDR_DM2
M1_DDR_DQ14
M1_DDR_DQ28
M1_DDR_DQS_N0
M0_DDR_A6
M0_DDR_DQ27
M0_DDR_A11
M1_DDR_DQ5
M1_DDR_DQ10
M1_DDR_DQ6
M1_DDR_A14
M0_DDR_A2
R541
10K
M1_DDR_DQ12
M0_U_CLKN
M0_DDR_VREFCA
M1_DDR_DQ15
M0_DDR_DQ23
M1_DDR_DQ13
M0_DDR_DQ3
VDDC15_M0
M1_DDR_DM3
M1_1_DDR_VREFCA
M1_DDR_A11
M1_DDR_CKE
M1_D_CLKN
M0_DDR_A7
M0_DDR_A12
M0_1_DDR_VREFDQ
M0_DDR_DQS1
R516
1K1%
C509
0.1uF
M0_DDR_A11
VDDC15_M1
R518
100
R514
1K1%
M1_DDR_DQS1 M1_DDR_DQS3
M1_DDR_CKE
M0_DDR_CASN
M1_DDR_A7
M0_DDR_DQS3
M0_DDR_BA0
M0_DDR_DQS_N0
R520
10K
M0_DDR_A1
M1_DDR_DQ11
M1_DDR_A1
M1_DDR_BA2
M0_DDR_DQS_N2
C504
0.1uF
M0_DDR_DM1
M1_DDR_A11
M1_DDR_DQ22
M0_D_CLKN
M1_DDR_A0
M0_DDR_DQ30
M1_DDR_A15
M1_1_DDR_VREFDQ
R538
1K1%
M0_DDR_DQ18
M0_DDR_DQ0
M1_DDR_A8
M1_DDR_DQ25
M0_DDR_BA2
VDDC15_M1
M0_DDR_DQ24
R532
1K 1%
M1_DDR_BA0
M1_DDR_DQ26
M0_DDR_A8
M0_DDR_RASN
M1_DDR_A2
M1_DDR_A6
M0_U_CLK
R533
1K1%
M0_DDR_VREFDQ
M1_DDR_VREFDQ
VDDC15_M0
M1_DDR_A9
M1_DDR_DQ16
M0_DDR_DQ29
M1_DDR_A12
M1_DDR_A5
VDDC15_M0
M1_DDR_DQ12
M1_U_CLKN
M1_DDR_RASN
M0_DDR_DM0
M0_DDR_DQ15
M0_DDR_DQ6
C566 0.1uF
M0_DDR_A2
M1_DDR_A3
M1_DDR_DQ8
M0_DDR_DQ9
M0_DDR_DQ20
R501
240
1%
M1_D_CLK
M0_DDR_BA0
M1_DDR_DM2
M0_DDR_DQ30
M0_DDR_DQ27
M1_DDR_VREFCA
M0_D_CLK
C530 0.1uF
M0_DDR_DQ22
M0_DDR_A2
M1_DDR_A13
M0_DDR_BA0
C505
0.1uF
M1_DDR_CASN
M0_1_DDR_VREFCA
C512
0.1uF
R545 240
M0_DDR_DQ17
M0_DDR_DQ15
M1_DDR_DQ0
M1_DDR_A1
M0_DDR_ODT
M1_DDR_BA1
M1_DDR_DQ25
M0_DDR_WEN
M1_DDR_DQ29
M1_DDR_VREFDQ
M1_DDR_DQ9
M0_DDR_DM1
M0_DDR_DQ0
M0_DDR_DQ2
M1_DDR_A7
M1_DDR_DQ21
M0_1_DDR_VREFCA
M0_DDR_A4
M1_DDR_DQ13
M0_DDR_CASN
M1_DDR_A11
C529 0.1uF
M1_DDR_DQ16
C567 0.1uF
M0_DDR_DQ5
M0_DDR_DQ14
M1_DDR_DM2
M1_DDR_DM0
M1_DDR_A0
M0_DDR_A0
M0_DDR_DQS_N1
M1_DDR_DQ10
M1_DDR_A5
M1_U_CLK
M0_DDR_DM0
M1_DDR_DQ18
M0_DDR_DQS_N0
M0_DDR_VREFCA
R535
100
M0_DDR_DQ6
M1_DDR_A7
M1_D_CLKN
M0_DDR_DQ21
VDDC15_M1
M0_DDR_A10
M1_DDR_DQ7
C513
0.1uF
M1_U_CLK
M1_DDR_DQ2
VDDC15_M0
M1_DDR_A10
M0_DDR_A8
M1_DDR_DQ14
M1_DDR_RESET_N
M0_DDR_DQ1
M0_DDR_DQ29
M0_DDR_DQS2
M0_DDR_A13
M1_DDR_A15
M0_DDR_DQS1
M1_DDR_DQ17
R537
1K 1%
M1_DDR_DQ1
M0_DDR_RESET_N
M1_DDR_A10
M1_DDR_A8
M1_DDR_BA1
M1_DDR_DQS_N2
M1_U_CLKN
M0_DDR_A5
M1_DDR_DQ23
M0_DDR_DM3
M0_DDR_DQ19
VDDC15_M0
R512
1K1%
M1_DDR_CASN
M0_DDR_DQ8
M0_U_CLKN
M0_DDR_DQ22
M1_DDR_A13
M1_DDR_BA2
M0_DDR_BA1
M0_DDR_A15
M0_DDR_DM2
M0_DDR_A9
M1_DDR_DQS_N2
M0_DDR_DQ1
M1_DDR_WEN
M0_DDR_A4
M1_DDR_A4
M1_DDR_DQ5
M1_DDR_A9
M0_DDR_CKE
M0_DDR_DQ16
M0_DDR_A9
M1_DDR_DM1
M0_DDR_DQ5
M1_DDR_A1
R539
1K 1%
C508
0.1uF
M1_DDR_DQ24
M0_DDR_DQ18
M0_U_CLKN
VDDC15_M0
M0_1_DDR_VREFDQ
M1_DDR_DQ31
M1_DDR_DQ21
M0_DDR_CKE
M0_DDR_DQ31
M0_DDR_A15
M0_DDR_DQ8
M0_DDR_DQ13
M0_DDR_A15
M0_DDR_DQ19
M1_1_DDR_VREFCA
M0_D_CLK
M0_DDR_DQ7
M1_DDR_A3
M0_DDR_RASN
M1_DDR_A14
M1_DDR_DQS_N1
M1_DDR_ODT
M1_DDR_DQS2
R511
1K 1%
M0_DDR_WEN
M1_DDR_DQ4
M1_DDR_A2
M0_DDR_DQ12
M0_DDR_A14
M1_DDR_A8
M0_DDR_DQ28
M0_DDR_DQS_N3
R521
10K
R536
1K1%
M1_DDR_DQ11
M1_DDR_DQ6
M0_DDR_A6
M1_DDR_VREFCA
M0_DDR_DQ3
M1_DDR_DQ27
M0_DDR_A5
M0_DDR_DQ4
M1_DDR_BA0
M0_DDR_DQ7
M0_DDR_A14
M1_DDR_DQ15
R510
1K1%
M1_DDR_DQ26
M1_DDR_A0
M0_D_CLKN
M1_DDR_A4
M0_DDR_A1
VDDC15_M1
M0_DDR_A0
M1_DDR_DQ22
M0_DDR_CKE
M0_DDR_WEN
VDDC15_M1
M1_DDR_A2
M1_DDR_A3
M1_DDR_DQ17
M1_D_CLK
M1_DDR_DM3
M1_DDR_DQS3
M0_DDR_A12
M0_U_CLK
M1_DDR_DQ30
M1_D_CLK
M0_DDR_A10
R515
1K 1%
M1_DDR_CKE
M0_DDR_DQ31
M0_DDR_ODT
M0_DDR_RESET_N
M0_DDR_A0
M1_DDR_DQS_N3
M0_DDR_DQ24
M1_DDR_DQ2
M0_DDR_CKE
M1_DDR_RESET_N
M1_DDR_A15
M1_DDR_ODT
M1_DDR_DQ19
R517
1K 1%
M1_DDR_CASN
M0_DDR_A13
M0_D_CLK
M0_DDR_DQS0
M0_DDR_DQS_N3
M0_DDR_DQS3
R531
1K1%
M1_DDR_DQ1
M1_DDR_A12
M0_DDR_DQS_N2
M0_DDR_DQ13
M1_DDR_A9
M0_DDR_A13
M1_DDR_DM0
M0_DDR_BA2
M1_DDR_BA1
M1_DDR_DQ9
M0_DDR_A5
C562 0.1uF
M0_DDR_A9
M0_DDR_DQ2
M1_DDR_DQ3
M0_DDR_DQ11
M1_D_CLKN
M0_DDR_DQS0
M1_DDR_DQ0
M1_DDR_BA2
R519
100
C500
0.1uF
M1_DDR_DQ23
M1_DDR_ODT
M1_DDR_DQ27
M1_DDR_DQ8
M0_U_CLK
M1_DDR_DQS1
M0_DDR_A1
M0_DDR_BA1
M1_DDR_A10
M1_DDR_DQ24
M0_DDR_A10
R530
100
M0_DDR_DQ20
M1_DDR_A14
VDDC15_M0
M0_DDR_A3
M1_DDR_BA0
M1_DDR_DQS_N3
M0_DDR_DM3
M1_DDR_A6
M1_DDR_RESET_N
M0_DDR_RASN
M0_DDR_A7
M0_DDR_DQ28
M0_DDR_RESET_N
R540
10K
M0_DDR_DQ23
R500
240
1%
M0_DDR_BA1
M0_DDR_DQ21
M0_DDR_DQ9
M1_DDR_DQS0
M0_DDR_DQS_N1
M1_DDR_DQ20
M0_DDR_DQ16
M1_U_CLK
M1_1_DDR_VREFDQ
M1_DDR_DQ31
M1_DDR_A12
R543 240
M0_DDR_A8
M0_DDR_A7
M0_DDR_DQ12
VDDC15_M1
M1_U_CLKN
M1_DDR_DQS2
M1_DDR_DQS_N0
M1_DDR_WEN
M0_DDR_A12
M0_DDR_A14
M1_DDR_RASN
M0_DDR_DQ17
R534
1K 1%
M0_D_CLKN
M1_DDR_A4
R542
240
1%
M0_DDR_BA2
M0_DDR_A11
M0_DDR_A3
C534 0.1uF
K4B4G1646B-HCK0

IC500

DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
A14
T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
K4B4G1646B-HCK0

IC501

DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
A14
T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
K4B4G1646B-HCK0

IC503

DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
A14
T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
K4B4G1646B-HCK0

IC502

DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQ L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
A14
T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
H5TQ4G63AFR-PBC
IC500-*1
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCAM8
VREFDQH1
ZQL8
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
NC_1J1
NC_2J9
NC_3L1
NC_4L9
A14
T7
VSS_1A9
VSS_2B3
VSS_3E1
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
H5TQ4G63AFR-PBC
IC502-*1
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCAM8
VREFDQH1
ZQL8
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
NC_1J1
NC_2J9
NC_3L1
NC_4L9
A14
T7
VSS_1A9
VSS_2B3
VSS_3E1
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
H5TQ4G63AFR-PBC
IC503-*1
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCAM8
VREFDQH1
ZQL8
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
NC_1J1
NC_2J9
NC_3L1
NC_4L9
A14
T7
VSS_1A9
VSS_2B3
VSS_3E1
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9
H5TQ4G63AFR-PBC
IC501-*1
DDR_HYNIX
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCAM8
VREFDQH1
ZQL8
VDD_1B2
VDD_2D9
VDD_3G7
VDD_4K2
VDD_5K8
VDD_6N1
VDD_7N9
VDD_8R1
VDD_9R9
VDDQ_1A1
VDDQ_2A8
VDDQ_3C1
VDDQ_4C9
VDDQ_5D2
VDDQ_6E9
VDDQ_7F1
VDDQ_8H2
VDDQ_9H9
NC_1J1
NC_2J9
NC_3L1
NC_4L9
A14
T7
VSS_1A9
VSS_2B3
VSS_3E1
VSS_4G8
VSS_5J2
VSS_6J8
VSS_7M1
VSS_8M9
VSS_9P1
VSS_10P9
VSS_11T1
VSS_12T9
VSSQ_1B1
VSSQ_2B9
VSSQ_3D1
VSSQ_4D8
VSSQ_5E2
VSSQ_6E8
VSSQ_7F9
VSSQ_8G1
VSSQ_9G9

IC100

LG1154D_H13D

M0_DDR_A[0] F15
M0_DDR_A[1] F13
M0_DDR_A[2] F17
M0_DDR_A[3] F19
M0_DDR_A[4] E10
M0_DDR_A[5] E18
M0_DDR_A[6] E11
M0_DDR_A[7] F18
M0_DDR_A[8] F11
M0_DDR_A[9] F16
M0_DDR_A[10] E9
M0_DDR_A[11] E12
M0_DDR_A[12] E13
M0_DDR_A[13] E16
M0_DDR_A[14] F12
M0_DDR_A[15] F14
M0_DDR_BA[0] E19
M0_DDR_BA[1] F10
M0_DDR_BA[2] E15
M0_DDR_U_CLK B10
M0_DDR_U_CLKN A10
M0_DDR_D_CLK A19
M0_DDR_D_CLKN B19
M0_DDR_CKE E14
M0_DDR_ODT F21
M0_DDR_RASN E21
M0_DDR_CASN E20
M0_DDR_WEN F20
M0_DDR_RESET_N E17
M0_DDR_ZQCAL F9
M0_DDR_DQS[0] B20
M0_DDR_DQS_N[0] A20
M0_DDR_DQS[1] C19
M0_DDR_DQS_N[1] D19
M0_DDR_DQS[2] A11
M0_DDR_DQS_N[2] B11
M0_DDR_DQS[3] C10
M0_DDR_DQS_N[3] D10
M0_DDR_DM[0] D18
M0_DDR_DM[1] C20
M0_DDR_DM[2] D9
M0_DDR_DM[3] C11
M0_DDR_DQ[0] D22
M0_DDR_DQ[1] C15
M0_DDR_DQ[2] C23
M0_DDR_DQ[3] D16
M0_DDR_DQ[4] B24
M0_DDR_DQ[5] B15
M0_DDR_DQ[6] D23
M0_DDR_DQ[7] A15
M0_DDR_DQ[8] C16
M0_DDR_DQ[9] D21
M0_DDR_DQ[10] D17
M0_DDR_DQ[11] C22
M0_DDR_DQ[12] C18
M0_DDR_DQ[13] C21
M0_DDR_DQ[14] C17
M0_DDR_DQ[15] D20
M0_DDR_DQ[16] C13
M0_DDR_DQ[17] D7
M0_DDR_DQ[18] D13
M0_DDR_DQ[19] C6
M0_DDR_DQ[20] D14
M0_DDR_DQ[21] D6
M0_DDR_DQ[22] C14
M0_DDR_DQ[23] A5
M0_DDR_DQ[24] C7
M0_DDR_DQ[25] D12
M0_DDR_DQ[26] D8
M0_DDR_DQ[27] B13
M0_DDR_DQ[28] C9
M0_DDR_DQ[29] C12
M0_DDR_DQ[30] C8
M0_DDR_DQ[31] D11

IC100

LG1154D_H13D

M1_DDR_A[0] N6
M1_DDR_A[1] R6
M1_DDR_A[2] L6
M1_DDR_A[3] J6
M1_DDR_A[4] U5
M1_DDR_A[5] J5
M1_DDR_A[6] T5
M1_DDR_A[7] K6
M1_DDR_A[8] U6
M1_DDR_A[9] M6
M1_DDR_A[10] V5
M1_DDR_A[11] R5
M1_DDR_A[12] P5
M1_DDR_A[13] L5
M1_DDR_A[14] T6
M1_DDR_A[15] P6
M1_DDR_BA[0] H5
M1_DDR_BA[1] V6
M1_DDR_BA[2] M5
M1_DDR_U_CLK R2
M1_DDR_U_CLKN R1
M1_DDR_D_CLK F1
M1_DDR_D_CLKN F2
M1_DDR_CKE N5
M1_DDR_ODT G6
M1_DDR_RASN F5
M1_DDR_CASN G5
M1_DDR_WEN H6
M1_DDR_RESET_N K5
M1_DDR_ZQCAL F6
M1_DDR_DQS[0] E2
M1_DDR_DQS_N[0] E1
M1_DDR_DQS[1] F3
M1_DDR_DQS_N[1] F4
M1_DDR_DQS[2] P1
M1_DDR_DQS_N[2] P2
M1_DDR_DQS[3] R3
M1_DDR_DQS_N[3] R4
M1_DDR_DM[0] G4
M1_DDR_DM[1] E3
M1_DDR_DM[2] T4
M1_DDR_DM[3] P3
M1_DDR_DQ[0] C4
M1_DDR_DQ[1] K3
M1_DDR_DQ[2] B3
M1_DDR_DQ[3] J4
M1_DDR_DQ[4] A3
M1_DDR_DQ[5] K2
M1_DDR_DQ[6] B4
M1_DDR_DQ[7] K1
M1_DDR_DQ[8] J3
M1_DDR_DQ[9] D4
M1_DDR_DQ[10] H4
M1_DDR_DQ[11] C3
M1_DDR_DQ[12] G3
M1_DDR_DQ[13] D3
M1_DDR_DQ[14] H3
M1_DDR_DQ[15] E4
M1_DDR_DQ[16] M3
M1_DDR_DQ[17] V4
M1_DDR_DQ[18] M4
M1_DDR_DQ[19] W3
M1_DDR_DQ[20] L4
M1_DDR_DQ[21] W4
M1_DDR_DQ[22] L3
M1_DDR_DQ[23] Y2
M1_DDR_DQ[24] V3
M1_DDR_DQ[25] N4
M1_DDR_DQ[26] U4
M1_DDR_DQ[27] M2
M1_DDR_DQ[28] T3
M1_DDR_DQ[29] N3
M1_DDR_DQ[30] U3
M1_DDR_DQ[31] P4
MAIN DDR

H5TQ1G63DFR-PBC(x16)

DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)

4Gbit : T7(A14)

DDR3 1.5V bypass Cap - Place these caps near Memory

1Gbit : T7(NC_6)

Real USE : 1Gbit

DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
2012-09-14BSD-NC4_H005-HD
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only