Block Diagram for Backlight

SoC 3D

Chip

Main

UD@60Hz
Dual-Link LVDS For Video
UD@60Hz
Dual-Link LVDS For OSD
FRC3 FPGA
PA138
PA138
FPGA
FPGA
TCON
THC
216
THC
216
THC
215
THC
215
LVDS
LVDS
LVDS
LVDS
LVDS Vx1
Vx1
Vx1
Vx1
LVDS
LVDS
Bypass Bypass
Vx1 to LVDS
Interface
Formatter
Interface
Formatter
Vx1 to LVDS
LVDS to Vx1
LVDS to Vx1
3840x2160
1920x2160
1920x2160
3840x1080
(1920x2160) 1920x2160 1920x2160
1920x2160 1920x2160
3840x1080
(1920x2160)
3840x1080
(1920x2160)
3840x1080
(1920x2160)
4 Ch.
2 Ch.
2 Ch.
8 Ln.
8 Ln.
8 Ch.
8 Ch.
8 Ch.
8 Ch.
8 Ln.
8 Ln.
Interface resolution
(Image resolution)
Frame
Repeater
Frame
Repeater

[ 84LM960V Edge LED Backlight]

SPI/Vsync LED BLU control
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only