THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R154
100
1%
R162 33
RXBCLKP
+3.3V_IO
+3.3V_IO
R166
10K
R125 33
RXA3N
FLASH_WP
RXA2N
I2C_SDA_PQ
C120 0.1uF
+0.9VDC
TDO
C125
0.1uF
16V
C154
10uF
25V
RXA1N
+3.3V
R120
100
1%
RXB2P
R134 0
RXACLKP
C112 0.1uF
P102
12507WR-04L
1
2
3
4
5
I2C_SDA_S
I2C_SDA_PQ
RXA1P
R169
47K
OPT
I2C_SDA_S
R181 33
RXB2N
TCK
R110
100
1%
+0.9VDC
R172
4.7K
R178 0
C148
10uF
25V
XTAL_OUT
R118
100
1%
R152 33
TMS
R130 33
RXB0N
+3.3V
R175
1K
SPI_SCLK
C115 0.1uF
I2C_SCL_PQ
C118 0.1uF
+3.3V
P103
12507WR-04L
1
2
3
4
5
+1.8LVDS_TX
R124 33
SPI_DI
+3.3V
TX5P
RXB4P
SPI_CS
R135 0
C100
27pF
50V
R173
4.7K
+0.9AVDD
TX7P
C114 0.1uF
C122 0.1uF
3.3K
R102
XTAL_IN
R117
100
1%
+3.3V
+1.8V
I2C_SCL_S
R127 33
+1.8LVDS_RX
R105
3.3K
R167
47K
TDI
RXBCLKN
SPI_CS
TDO
TX7N
R115
100
1%
TX0N
+3.3V
RXB3N
TX2N
+0.9AVDD
RXB4N
C116 0.1uF
R155
100
1%
R129 33
R156 33 OPT
C113 0.1uF
XTAL_IN
+0.9VDC
FLASH_WP
C151
10uF
25V
C103
33pF
50V
OPT
C159
0.1uF
16V
R148 33OPT
C162
0.1uF
16V
R101 10K
C111 0.1uF
+1.8LVDS_RX
C149
0.1uF
16V
SPI_DO
R158
10K
OPT

IC101

MX25L3206EM2I-12G

SPI_FLASH
3
WP#
2
SO/SIO1
4
GND
1
CS#
5SI/SIO0
6SCLK
7HOLD#
8VCC
R104
3.3K
3D_LR
UART_TX
R128 33
TDI
R133 0
+3.3V_IO
RXA0P
SPI_SCLK
C104
27pF
50V
C109 0.1uF
SPI_DL_MODE
C163
0.1uF
16V
R176 0
OPT
R149 33
UART_TX
SPI_DI
P100
12507WR-10L
1
2
3
4
5
6
7
8
9
10
11
SPI_DO
SPI_DO
C121 0.1uF
R150 33OPT
R180 33
TX3P
R121
100
1%
TX5N
R131 33
TX_LOCK
C119 0.1uF
+1.8LVDS_RX
+0.9VDC
C107
33pF
50V
OPT
C161
0.1uF
16V
UART_RX
SPI_CS
TX6P
C105
33pF
50V
OPT
TX0P
FLASH_WP
RXA4N
LG1122_RST
+3.3V
R122
100
1%
RXA0N
R163 33OPT
RXB3P
SPI_DL_MODE
RXB1N
R177 0
OPT
SPI_SCLK
C108 0.1uF
R138 33 OPT
SW100
JTP-1127WEM
12
4 3
R153 33
R136 33 OPT
TX1N
+1.8LVDS_TX
RXB1P
RXA4P
UART_RX
R174
3.3K
+0.9AVDD
R159
33
RXB0P
RBF
R179 0
R123
100
1%
R183 33
+1.8LVDS_TX
R103
3.3K
AGP_EN
R160 33
I2C_SCL_PQ
C110 0.1uF
R168
10K
R161 33
TRST_N
3D_EN
TRST_N
R113
10K
P101
12507WR-08L
1
2
3
4
5
6
7
8
9
TCK
R109
100
1%
R114
100
1%
R106
1M
TX4P
RXA2P
SPI_DI
+3.3V
TX4N
+0.9VDC
R157
4.7K
TX3N
R139 0OPT
TX6N
TX2P
+1.8V
RXACLKN
R132 33
I2C_SCL_S
TX1P
+1.8V
C157
10uF
25V
R182 33
RXA3P
R126 33
C123 0.1uF
C124
0.1uF
R137 33 OPT
+1.8V_AVDD
+1.8LVDS_RX
TMS
R151 33OPT
XTAL_OUT
C117 0.1uF
R146 33
+0.9V
PWM_BPL
R164 33
R165 33
+3.3V
R112
1K
R111
1K
L102
MLB-201209-0120P-N2
L100
MLB-201209-0120P-N2
L101
MLB-201209-0120P-N2
L103
MLB-201209-0120P-N2 L105
MLB-201209-0120P-N2
C126
4.7uF
10V
C127
4.7uF
10V
C129
4.7uF
10V
C131
4.7uF
10V
C134
4.7uF
10V
C135
4.7uF
10V
C137
4.7uF
10V
C139
4.7uF
10V
C144
4.7uF
10V
C153
4.7uF
10V
+1.8V
C142
4.7uF
10V
C152
4.7uF
10V
L104
MLB-201209-0120P-N2
+1.8V_AVDD +1.8V_AVDD
C158
0.1uF
16V
R185
10K
OPT
+3.3V
3.3K
R186
OPT
L/DIM0_SCLK
L/DIM0_MOSI
L/DIM0_VS
R107
10K
120Hz
R108
10K
W/O_TCON
+3.3V
R116
10K
W_TCON
R119
10K
240Hz
+3.3V
SOC_OPT
+3.3V
R170
10K
L9(LG1152)
R171
10K
MTK
SOC_OPT
FRAME_OPT
DISPLAY_OPT
REVERSE_OPT
TCON_OPT
TCON_OPTFRAME_OPT
+3.3V
R189
10K
OLED
R190
10K
LCD
R187
10K
IMAGE_NORMAL
+3.3V
R188
10K
IMAGE_REVERSE
REVERSE_OPT DISPLAY_OPT
R191 0
IC100
LG1122
RXA0P
AC1
RXA0N
AC2
RXA1P
AB3
RXA1N
AC3
RXA2P
AB2
RXA2N
AB1
RXACLKP
AA1
RXACLKN
AA2
RXA3P
Y3
RXA3N
AA3
RXA4P
Y2
RXA4N
Y1
RXB0P
W1
RXB0N
W2
RXB1P
V3
RXB1N
W3
RXB2P
V2
RXB2N
V1
RXBCLKP
U1
RXBCLKN
U2
RXB3P
T3
RXB3N
U3
RXB4P
T2
RXB4N
T1
L_VSOUT_LD
B26
R_VSOUT_LD
E2
M0_SCLK
C26
M0_MOSI
E22
M1_SCLK
D24
M1_MOSI
G22
M2_SCLK
D2
M2_MOSI
E1
M3_SCLK
D1
M3_MOSI
D3
UART_RXD
G3
UART_TXD
H3
SPI_SCLK
G1
SPI_CS
G2
SPI_DI
F2
SPI_DO
F1
SDA_M
J1
SCL_M
J2
SDA_S
H1
SCL_S
H2
SMODE
K2
TMODE0
J3
TMODE1
K3
TMODE2
L3
TMODE3
M3
TRST_N
M2
TDO
L1
TDI
L2
TCLK
M1
TMS
N1
PORES_N
K1
XTALO
AF6
XTALI
AE6
MON_SYNC0
N2
MON_SYNC1
N3
MON_INTR
P3
VIREF_REXT
C1
TX_LOCKN
C2
GPIO[0]
AB5
GPIO[1]
AB4
GPIO[2]
AD5
GPIO[3]
AC5
GPIO[4]
AE4
GPIO[5]
AD4
GPIO[6]
AC4
GPIO[7]
AF3
GPIO[8]
AE3
GPIO[9]
AD3
GPIO[10]
AF2
GPIO[11]
AE2
GPIO[12]
AD2
GPIO[13]
AE1
GPIO[14]
B25
GPIO[15]
B24
TX0P B2
TX0N A2
TX1P A3
TX1N B3
TX2P C4
TX2N C3
TX3P B4
TX3N A4
TX4P A5
TX4N B5
TX5P C6
TX5N C5
TX6P B6
TX6N A6
TX7P A7
TX7N B7
TXA0P A23
TXA0N B23
TXA1P C22
TXA1N C23
TXA2P B22
TXA2N A22
TXACLKP A21
TXACLKN B21
TXA3P C20
TXA3N C21
TXA4P B20
TXA4N A20
TXB0P A19
TXB0N B19
TXB1P C18
TXB1N C19
TXB2P B18
TXB2N A18
TXBCLKP A17
TXBCLKN B17
TXB3P C16
TXB3N C17
TXB4P B16
TXB4N A16
TXC0P A15
TXC0N B15
TXC1P C14
TXC1N C15
TXC2P B14
TXC2N A14
TXCCLKP A13
TXCCLKN B13
TXC3P C12
TXC3N C13
TXC4P B12
TXC4N A12
TXD0P A11
TXD0N B11
TXD1P C10
TXD1N C11
TXD2P B10
TXD2N A10
TXDCLKP A9
TXDCLKN B9
TXD3P C8
TXD3N C9
TXD4P B8
TXD4N A8
GPIO[16] C25
GPIO[17] C24
GPIO[18] AD1
GPIO[19] R1
GPIO[20] R2
GPIO[21] R3
GPIO[22] P1
GPIO[23] A25
GPIO[24] D23
GPIO[25] D22
GPIO[26] F22
GPIO[27] E23
GPIO[28] E3
GPIO[29] F3
GPIO[30] A24
GPIO[31] P2
IC100
LG1122
VSS_1
B1
VSS_2
C7
VSS_3
D4
VSS_4
D5
VSS_5
D6
VSS_6
D7
VSS_7
D8
VSS_8
D18
VSS_9
D19
VSS_10
D20
VSS_11
D21
VSS_12
D25
VSS_13
D26
VSS_14
E4
VSS_15
E5
VSS_16
E6
VSS_17
E7
VSS_18
E8
VSS_19
E9
VSS_20
E10
VSS_21
E11
VSS_22
E12
VSS_23
E13
VSS_24
E14
VSS_25
E15
VSS_26
E16
VSS_27
E17
VSS_28
E18
VSS_29
E19
VSS_30
E21
VSS_31
E24
VSS_32
F5
VSS_33
F7
VSS_34
F8
VSS_35
F9
VSS_36
F10
VSS_37
F11
VSS_38
F12
VSS_39
F13
VSS_40
F14
VSS_41
F15
VSS_42
F16
VSS_43
F17
VSS_44
F18
VSS_45
F19
VSS_46
F21
VSS_47
F23
VSS_48
G5
VSS_49
G21
VSS_50
G23
VSS_51
H5
VSS_52
H8
VSS_53
H9
VSS_54
H10
VSS_55
H11
VSS_56
H12
VSS_57
H13
VSS_58
H14
VSS_59
H15
VSS_60
H16
VSS_61
H17
VSS_62
H18
VSS_63
H19
VSS_64
H21
VSS_65
H22
VSS_66
H23
VSS_67
J5
VSS_68
J8
VSS_69
J19
VSS_70
J21
VSS_71
J22
VSS_72
K4
VSS_73
K5
VSS_74
K8
VSS_75
K10
VSS_76
K11
VSS_77
K12
VSS_78
K13
VSS_79
K14
VSS_80
K15
VSS_81
K16
VSS_82
K17
VSS_83
K19
VSS_84
K21
VSS_85
K22
VSS_86
L4
VSS_87
L5
VSS_88
L8
VSS_89
L10
VSS_90
L11
VSS_91
L12
VSS_92
L13
VSS_93
L14
VSS_94
L15
VSS_95
L16
VSS_96
L17
VSS_97
L19
VSS_98
L21
VSS_99
L22
VSS_100
M4
VSS_101
M5
VSS_102
M6
VSS_103
M8
VSS_104
M10
VSS_105
M11
VSS_106
M12
VSS_107
M13
VSS_108
M14
VSS_109
M15
VSS_110
M16
VSS_111
M17
VSS_112
M19
VSS_113
M21
VSS_114
M22
VSS_115
N4
VSS_116
N5
VSS_117
N6
VSS_118
N8
VSS_119
N10
VSS_120
N11
VSS_121
N12
VSS_122
N13
VSS_123
N14
VSS_124
N15
VSS_125
N16
VSS_126
N17
VSS_127
N19
VSS_128
N21
VSS_129
N22
VSS_130
N24
VSS_131
P4
VSS_132
P5
VSS_133
P6
VSS_134
P8
VSS_135 P10
VSS_136 P11
VSS_137 P12
VSS_138 P13
VSS_139 P14
VSS_140 P15
VSS_141 P16
VSS_142 P17
VSS_143 P19
VSS_144 P21
VSS_145 P22
VSS_146 P24
VSS_147 R4
VSS_148 R5
VSS_149 R6
VSS_150 R8
VSS_151 R10
VSS_152 R11
VSS_153 R12
VSS_154 R13
VSS_155 R14
VSS_156 R15
VSS_157 R16
VSS_158 R17
VSS_159 R19
VSS_160 R21
VSS_161 R22
VSS_162 T5
VSS_163 T6
VSS_164 T8
VSS_165 T10
VSS_166 T11
VSS_167 T12
VSS_168 T13
VSS_169 T14
VSS_170 T15
VSS_171 T16
VSS_172 T17
VSS_173 T19
VSS_174 T21
VSS_175 T22
VSS_176 U5
VSS_177 U6
VSS_178 U8
VSS_179 U10
VSS_180 U11
VSS_181 U12
VSS_182 U13
VSS_183 U14
VSS_184 U15
VSS_185 U16
VSS_186 U17
VSS_187 U19
VSS_188 U21
VSS_189 U22
VSS_190 V5
VSS_191 V6
VSS_192 V8
VSS_193 V19
VSS_194 V21
VSS_195 V22
VSS_196 W5
VSS_197 W6
VSS_198 W8
VSS_199 W9
VSS_200 W10
VSS_201 W11
VSS_202 W12
VSS_203 W13
VSS_204 W14
VSS_205 W15
VSS_206 W16
VSS_207 W17
VSS_208 W18
VSS_209 W19
VSS_210 W21
VSS_211 W22
VSS_212 Y4
VSS_213 Y5
VSS_214 Y21
VSS_215 Y22
VSS_216 AA4
VSS_217 AA7
VSS_218 AA8
VSS_219 AA9
VSS_220 AA10
VSS_221 AA11
VSS_222 AA12
VSS_223 AA13
VSS_224 AA14
VSS_225 AA15
VSS_226 AA16
VSS_227 AA17
VSS_228 AA18
VSS_229 AA19
VSS_230 AA20
VSS_231 AA21
VSS_232 AA22
VSS_233 AA23
VSS_234 AB6
VSS_235 AB7
VSS_236 AB8
VSS_237 AB9
VSS_238 AB10
VSS_239 AB11
VSS_240 AB12
VSS_241 AB13
VSS_242 AB14
VSS_243 AB15
VSS_244 AB16
VSS_245 AB17
VSS_246 AB18
VSS_247 AB19
VSS_248 AB20
VSS_249 AB21
VSS_250 AB22
VSS_251 AB23
VSS_252 AC6
VSS_253 AC7
VSS_254 AC8
VSS_255 AC9
VSS_256 AC10
VSS_257 AC23
VSS_258 AC24
VSS_259 AC25
VSS_260 AC26
VSS_261 AD6
VSS_262 AD7
VSS_263 AD8
VSS_264 AD17
VSS_265 AD18
VSS_266 AE8
VSS_267 AF4
VSS_268 AF8
IC100
LG1122
VDD_1
J9
VDD_2
J10
VDD_3
J11
VDD_4
J16
VDD_5
J17
VDD_6
J18
VDD_7
K9
VDD_8
K18
VDD_9
L9
VDD_10
L18
VDD_11
M9
VDD_12
M18
VDD_13
N9
VDD_14
N18
VDD_15
P9
VDD_16
P18
VDD_17
R9
VDD_18
R18
VDD_19
T9
VDD_20
T18
VDD_21
U9
VDD_22
U18
VDD_23
V9
VDD_24
V10
VDD_25
V11
VDD_26
V12
VDD_27
V13
VDD_28
V14
VDD_29
V15
VDD_30
V16
VDD_31
V17
VDD_32
V18
VDD33_1 F6
VDD33_2 F20
VDD33_3 G6
VDD33_4 H6
VDD33_5 J6
VDD33_6 K6
VDD33_7 L6
VDD33_8 Y6
VDD33_9 AA6
VDD18_1 E20
VDD18_2 F4
VDD18_3 G4
VDD18_4 H4
VDD18_5 J4
VDD18_6 AA5
LVRX_VDD18_1 T4
LVRX_VDD18_2 U4
LVRX_VDD18_3 V4
LVRX_VDD18_4 W4
LVTX_VDD18_1 D9
LVTX_VDD18_2 D10
LVTX_VDD18_3 D11
LVTX_VDD18_4 D12
LVTX_VDD18_5 D13
LVTX_VDD18_6 D14
LVTX_VDD18_7 D15
LVTX_VDD18_8 D16
LVTX_VDD18_9 D17
LVTX_VDD_1 J12
LVTX_VDD_2 J13
LVTX_VDD_3 J14
LVTX_VDD_4 J15
AVDD09_1 AE7
AVDD09_2 AF7
AVDD18_1 AE5
AVDD18_2 AF5
OPT_READY_1
OPT_READY_2
L/DIMMING_OPT
R142
10K
OPT
R144
10K
OPT
R143
10K R145
10K
+3.3V +3.3V
R140
10K
L/D_ON_FRC
R141
10K
L/D_ON_MAIN
OPT_READY_2
+3.3V
OPT_READY_1L/DIMMING_OPT
X100
24.75MHz
4GND_2
1
X-TAL_1
2
GND_1 3X-TAL_2
PANEL_CTL
R147
3.3K
FRC-III(LG1122) 1 6

XTAL(24.75MHz)

+3.3V Power Separation
RESET Input
1) LG1122_RST : From Main SOC
2) HW_RESET : From HW Switch
3) SPI_DL_MODE : Download Mode to Flash Mem
+0.9V Power SeparationSPI/I2C For Aardvak Interface+0.9VDC Decaps+3.3V_IO DecapsSPI FLASH(4MByte)+0.9AVDD Decaps+1.8VLVDS_RX DecapsUART For CPU
The Vx1_HS Tx AC-coupling Caps must be
placed near by LG1122
+1.8VLVDS_TX Decaps
GPIO[1:0]
: Local Dimming Debugging
GPIO[7:3] = PWM[4:0]
1) GPIO[3] : 120Hz Mode --> 60 or 120Hz (Programmable)
240Hz Mode --> 120 or 240Hz (Programmable)
2) GPIO[4] : 120Hz Mode --> 60 or 120Hz (Programmable)
240Hz Mode --> 120 or 240Hz (Programmable)
3) GPIO[5] : 120Hz Mode --> 120 or 240Hz (Programmable)
240Hz Mode --> 240 or 480Hz (Programmable)
4) GPIO[6] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
5) GPIO[7] : 120Hz Mode --> 120Hz (Fixed)
240Hz Mode --> 240Hz (Fixed)
GPIO[8]
: External Vsync input for Local Dimming block
GPIO[10]
: T-Con L/R Sync Monitor(AR)
GPIO[12:11]
: S/W I2C_Master CH
GPIO[26:16]
: BLU Direct Control CH
GPIO[28:27]
: I2C for PQ tunning
For JTAG InterfaceAll of OPT decaps must be placed on PCB Bottom side
Vx1_HS output swing level control
via external resistor
I2C For PQ tunning
I2C Slave Address
0x1C (Direct access)
0xB2 (In-direct access)
+1.8V Power Separation240Hz Back-End Board 2011. 07. 05
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
Will be deleted pull-up resistor from B0+3D Depth B’d

READY FOR H/W OPTION

OPT_READY_1
11
(for 72INCH)
JIG_OPT
240Hz
OPT_READY_2
With_TCON
IMAGE_OPT
OPTION NAME LOW
20
21
DISPLAY_OPT OLED
22
IMAGE_NORMAL
L/D_ON_FRC
OPT
L9 (LG1152)
120Hz
13
GPIO NO
15
MTK
OPT
FRAME_OPT
Default
Without_TCON
(for FRC3 JIG)
12
L/D_ON_MAIN
(for NON_72INCH)
IMAGE_OPT
SOC_OPT
Default
14
L/DIMMING_OPT
HIGH
LCD
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