LG Electronics 55LM860V/W-ZB, W-ZB FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS , DDR1 PHY VREFDDR0 PHY VREF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR0_DATA[14]
DDR0_A[0]
DDR0_A[7]
DDR1_A[0]
DDR0_A[6]
DDR0_DATA[12]
DDR1_A[2]
DDR0_DATA[10]
DDR1_DATA[1]
DDR0_DATA[8]
DDR1_DATA[12]
DDR1_DATA[14]
DDR0_A[10]
DDR0_DATA[11]
DDR0_DATA[4]
DDR0_A[5] DDR1_A[4]
DDR1_A[6]
DDR1_DATA[13]
DDR0_DATA[0]
DDR1_A[4]
DDR1_A[6]
DDR0_DATA[12]
DDR0_DATA[7]
DDR1_A[2]
DDR0_A[3]
DDR1_DATA[6]
DDR1_A[0]
DDR1_A[10]
DDR1_DATA[0]
DDR0_A[10]
DDR1_A[12]
DDR1_DATA[8]
DDR0_A[9]
DDR0_DATA[5]
DDR1_A[7]
DDR0_A[8]
DDR1_DATA[14]
DDR1_DATA[7]
DDR0_DATA[4]
DDR0_A[5]
DDR0_DATA[5]
DDR0_A[11]
DDR0_DATA[2]
DDR1_A[8]
DDR0_A[12]
DDR0_A[7]
DDR0_A[9]
DDR1_DATA[6]
DDR0_A[11]
DDR1_A[3]
DDR1_DATA[10]
DDR1_DATA[10]
DDR1_DATA[8]
DDR1_DATA[7]
DDR1_DATA[11]
DDR0_DATA[9]
DDR1_DATA[4]
DDR0_A[1]
DDR0_A[3]
DDR1_DATA[13]
DDR0_A[2]
DDR1_DATA[3]
DDR1_A[8]
DDR0_A[4]
DDR1_A[1]
DDR1_A[1]
DDR1_A[9]
DDR1_A[5]
DDR0_A[2]
DDR0_DATA[1]
DDR1_DATA[4]
DDR0_A[8]
DDR0_A[12]
DDR1_DATA[3]
DDR0_DATA[15]
DDR1_A[12]
DDR1_DATA[15]
DDR0_DATA[10]
DDR1_A[11]
DDR0_DATA[2]
DDR1_DATA[12]
DDR1_DATA[9]
DDR0_DATA[0]
DDR0_A[0]
DDR0_DATA[6]
DDR0_A[4]
DDR1_A[11]
DDR0_DATA[9]
DDR1_A[3]
DDR0_DATA[1]
DDR0_A[6]
DDR1_DATA[9]
DDR0_DATA[8]
DDR1_DATA[15]
DDR1_A[7]
DDR1_DATA[2]
DDR0_DATA[6]
DDR0_DATA[15]
DDR1_A[9]
DDR1_DATA[0]
DDR0_DATA[7]
DDR1_DATA[2]
DDR0_A[1]
DDR0_DATA[11]
DDR1_DATA[5]
DDR1_A[5]
DDR0_DATA[14]
DDR1_DATA[11]
DDR0_DATA[13]
DDR0_DATA[3]
DDR0_DATA[3]
DDR1_A[10]
DDR0_DATA[13]
DDR1_DATA[5]
DDR1_DATA[1]
DDR0_BA[2]
DDR1_CKE
R222 1001%
C237
0.1uF
DDR0_BA[0]
DDR1_DM[1]
R210
1K
1%
R216 240
1%
DDR0_RASN
DDR1_RASN
DDR0_WEN
C238
0.1uF
DDR0_A[0-12]
DDR1_DM[0]
DDR0_BA[1]
DDR0_RESET_N
+1.5V
C224
0.1uF
R207
1K
1%
+0.75V_VREF1_D0
C241
0.1uF
DDR1_DQS_N[1]
+1.5VQ1
DDR1_DATA[0-15]
R219
1K
1%
+0.75V_VREF1_M0
DDR1_A[0-12]
DDR1_BA[0]
+0.75V_VREF0_D1
DDR1_BA[1]
C203
0.1uF
C229
0.1uF C232 0.1uF
DDR1_RESET_N
C217
0.1uF
R209
1K
1%
+1.5VQ0
DDR1_DQS_N[0]
DDR0_BA[1]
DDR0_BA[0]
+1.5VQ0
DDR1_DQS[1]
C226
0.1uF
C236
0.1uF
DDR1_CASN
R205
1K
1%
C227
1000pF
DDR1_CASN
C209
0.1uF
DDR0_CLK DDR1_DQS[0]
+0.75V_VREF1_D1
DDR1_A[0-12]
DDR1_DATA[0-15]
DDR0_DATA[0-15]
+1.5VQ0
C228
0.1uF C230 1000pF
DDR0_CLKN
DDR1_WEN
C202
0.1uF
+0.75V_VREF0_D0
R217
1K
1%
C225
1000pF
DDR1_ODT
C223
0.1uF
C221
1000pF
+1.5VQ1
DDR1_BA[2]
DDR0_CKE
C201
0.1uF
R223
240 1%
DDR0_CLKN
DDR0_CLK
DDR1_RASN
DDR1_ODT
+1.5VQ0
+0.75V_VREF0_D0
R203
1K
1%
+1.5VQ1
DDR0_DATA[0-15]
R211 240
1%
+0.75V_VREF1_D1
DDR1_DQS_N[1]
+0.75V_VREF1_D0
C220
0.1uF
DDR1_CLK
C210
0.1uF
DDR0_DQS_N[1]
+1.5VQ0
DDR0_DM[0]
+1.5VQ1
DDR1_BA[2]
+1.5V
DDR0_ODT
DDR1_CKE
+1.5VQ1
+1.5VQ0
R204
1K
1%
DDR0_DQS[0]
DDR0_CASN
DDR1_BA[0]
DDR0_DQS[0]
DDR0_RASN
+0.75V_VREF0_D1
R208
1K
1%
C212
0.1uF
+0.75V_VREF1_M0
DDR1_CLKN
C218
1000pF
R202
240 1%
C216
0.1uF
DDR0_DQS_N[0] DDR0_DQS_N[0]
C204
0.1uF
DDR1_CLKN
DDR0_DQS[1]
R214
1K
1%
C206
0.1uF
+0.75V_VREF1_D1
+1.5VQ0
C215
1000pF
C214
0.1uF
+0.75V_VREF1_M1
DDR0_DM[0]
+1.5VQ1
R212
1K
1%
+1.5VQ0
DDR1_DM[0]
R206
1K
1%
DDR0_RESET_N
DDR0_DQS[1]
+0.75V_VREF0_M0
+0.75V_VREF0_M0
C233
1000pF
C242
0.1uF
DDR0_CKE
C213
1000pF
+0.75V_VREF1_M1
DDR0_A[0-12]
+1.5VQ1
DDR1_DQS[0]
DDR1_WEN
DDR1_RESET_N
+0.75V_VREF0_D1
R218
1K
1%
R215
1K
1%
C244
0.1uF
R201 1001%
DDR0_BA[2]
DDR0_DM[1]
+0.75V_VREF1_D0
+0.75V_VREF0_M1
C211
0.1uF
C235
0.1uF
DDR0_DQS_N[1]
DDR0_DM[1]
R220
1K
1%
DDR1_DQS[1]
DDR1_DM[1]
DDR0_ODT
DDR1_DQS_N[0]
+1.5VQ1
DDR1_CLK
R213
1K
1%
+0.75V_VREF0_M1
H5TQ1G63DFR-PBC
IC200
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQL8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
DDR0_CASN
+0.75V_VREF0_D0
DDR0_WEN
DDR1_BA[1]
+1.5VQ1
H5TQ1G63DFR-PBC
IC201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA M8
VREFDQ H1
ZQL8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8 R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
NC_6 T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9 P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4 D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
+1.5VQ0
L200
MLB-201209-0120P-N2 L201 MLB-201209-0120P-N2
C219
4.7uF
10V
C222
4.7uF
10V
C231
4.7uF
10V
C234
4.7uF
10V
IC100
LG1122
DDR0_A[0]
AB25
DDR0_A[1]
F26
DDR0_A[2]
AB24
DDR0_A[3]
Y24
DDR0_A[4]
G26
DDR0_A[5]
Y25
DDR0_A[6]
G25
DDR0_A[7]
Y26
DDR0_A[8]
G24
DDR0_A[9]
AA26
DDR0_A[10]
H26
DDR0_A[11]
F25
DDR0_A[12]
H24
DDR0_A[13]
AA25
DDR0_A[14]
F24
DDR0_DQ[0]
T26
DDR0_DQ[1]
L24
DDR0_DQ[2]
U24
DDR0_DQ[3]
K26
DDR0_DQ[4]
U26
DDR0_DQ[5]
K24
DDR0_DQ[6]
U25
DDR0_DQ[7]
K25
DDR0_DQ[8]
M25
DDR0_DQ[9]
R26
DDR0_DQ[10]
L26
DDR0_DQ[11]
T24
DDR0_DQ[12]
M26
DDR0_DQ[13]
R25
DDR0_DQ[14]
M24
DDR0_DQ[15]
R24
DDR0_CK
J26
DDR0_CK_N
J25
DDR0_DQS[0]
P26
DDR0_DQS_N[0]
P25
DDR0_DQS[1]
N26
DDR0_DQS_N[1]
N25
DDR0_CKE
J24
DDR0_WE_N
W24
DDR0_RAS_N
V24
DDR0_CAS_N
V25
DDR0_ODT
V26
DDR0_DM[0]
L25
DDR0_DM[1]
T25
DDR0_BA[0]
W25
DDR0_BA[1]
H25
DDR0_BA[2]
W26
DDR0_RST_N
AA24
DDR0_ZQ_CAL
E25
DDR0_VREF0
AB26
DDR0_VREF1
E26
DDR0_VDDQ_1
J23
DDR0_VDDQ_2
K23
DDR0_VDDQ_3
L23
DDR0_VDDQ_4
M23
DDR0_VDDQ_5
N23
DDR0_VDDQ_6
P23
DDR0_VDDQ_7
R23
DDR0_VDDQ_8
T23
DDR0_VDDQ_9
U23
DDR0_VDDQ_10
V23
DDR0_VDDQ_11
W23
DDR0_VDDQ_12
Y23
DDR1_A[0] AE9
DDR1_A[1] AF25
DDR1_A[2] AD9
DDR1_A[3] AD11
DDR1_A[4] AF24
DDR1_A[5] AE11
DDR1_A[6] AE24
DDR1_A[7] AF11
DDR1_A[8] AD24
DDR1_A[9] AF10
DDR1_A[10] AF23
DDR1_A[11] AE25
DDR1_A[12] AD23
DDR1_A[13] AE10
DDR1_A[14] AD25
DDR1_DQ[0] AF15
DDR1_DQ[1] AD20
DDR1_DQ[2] AD14
DDR1_DQ[3] AF21
DDR1_DQ[4] AF14
DDR1_DQ[5] AD21
DDR1_DQ[6] AE14
DDR1_DQ[7] AE21
DDR1_DQ[8] AE19
DDR1_DQ[9] AF16
DDR1_DQ[10] AF20
DDR1_DQ[11] AD15
DDR1_DQ[12] AF19
DDR1_DQ[13] AE16
DDR1_DQ[14] AD19
DDR1_DQ[15] AD16
DDR1_CK AF22
DDR1_CK_N AE22
DDR1_DQS[0] AF17
DDR1_DQS_N[0] AE17
DDR1_DQS[1] AF18
DDR1_DQS_N[1] AE18
DDR1_CKE AD22
DDR1_WE_N AD12
DDR1_RAS_N AD13
DDR1_CAS_N AE13
DDR1_ODT AF13
DDR1_DM[0] AE20
DDR1_DM[1] AE15
DDR1_BA[0] AE12
DDR1_BA[1] AE23
DDR1_BA[2] AF12
DDR1_RST_N AD10
DDR1_ZQ_CAL AD26
DDR1_VREF0 AF9
DDR1_VREF1 AE26
DDR1_VDDQ_1 AC11
DDR1_VDDQ_2 AC12
DDR1_VDDQ_3 AC13
DDR1_VDDQ_4 AC14
DDR1_VDDQ_5 AC15
DDR1_VDDQ_6 AC16
DDR1_VDDQ_7 AC17
DDR1_VDDQ_8 AC18
DDR1_VDDQ_9 AC19
DDR1_VDDQ_10 AC20
DDR1_VDDQ_11 AC21
DDR1_VDDQ_12 AC22
R221
150
R200
150
LG1122_DDR3 2 6
DDR3 1.5V beCaps - Place these caps near Memory
DDR1 PHY VREFDDR0 PHY VREF
DDR3 1.5V Decaps - Place these caps near Memory
DDR3 1.5V/0.75V Decap
- Place these caps near IC100
DDR3 1.5V/0.75V Decap
- Place these caps near IC100
240Hz Back-End Board 2011. 07. 05
Copyright © 2012 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only