Pulse Width Modulator

Block Diagram
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
250
Panasonic
Not using internal pullup func-
tion,Figuer10-2 connect the
external pullup registance
10.2 Block Diagram10.3 PWM Data Registers

All registers in PWM function cannot be written by byte (be word only). Read by

byte is possible.

Bits 7 to 0 of each of the seven PWM data registers (PWM0 to PWM6) hold the

8-bit pulsewidth modulated data to be written to the PWMs. The registers reset to

0, and they set to 1 when PWM output is high.

PWM0–PWM6: PWMn Data Registers x’007E70’ –x’007E7C’
Note: With a 4-MHz oscillator:
fPWM = fSYSCLK/16
Output pulse cycle = 28/fPWM = 341.3 µs
Minimum pulse width = 1/fPWM = 1.33 µs
tLOW = (PWMn + 1) × 0.67 µs
Figure 10-2 PWM Block Diagram
Bit:76543 210
PWMn7 PWMn6 PWMn5 PWMn4 PWMn3 PWMn2 PWMn1 PWMn0
Reset:00000000
R/W:RRRRRRRR
MUX
432
PnCNT
PWMn
(P15 - P17,
P20 - P23)
DAC output
I/O control
f
PWM
MSB
765 10
PWM0 - PWM6
x'007E70' - x'007E7C'
PWM (8-bit)
8
Port
PnDIR
Data bus
PnPUP