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Lucent Technologies MN10285K, MN102F75K, MN102F85K, MN102H75K 13 I2C Bus Controller

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I2C Bus Controller

Description

MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company

293

Panasonic

13 I2C Bus Controller

13.1 Description

The MN102H75K/85K contains one I2C bus controller, fully compliant with the

I2C specification, that can control one of two I2C bus connections.

An I2C bus is a simple, two-wire bus for transferring data between ICs. Since it

requires only two lines, a serial data line (SDA) and a serial clock line (SCL), it

minimizes interconnections so ICs have fewer pins and there are less PCB tracks.

The result is smaller and less expensive PCBs. Figure 13-1 shows a typical I2C

bus application.

In an I2C bus system, devices are considered as masters or slaves when performing

data transfers. A master is the device that initiates a data transfer on the bus and

generates the clock signals to permit that transfer. At that time, any device

addressed is considered a slave. Table 13-1 defines some I2C bus terminology.

Figure 13-1 Example of I2C Bus Application

Table 13-1 I2C Bus Terminology

Term Description

Transmitter The device that sends the data to the bus

Receiver The device that receives the data from the bus

Master The device that initiates a transfer, generates clock signals, and termi-

nates a transfer

Slave The device addressed by a master

Multimaster More than one device capable of controlling the bus can be connected

to it. More than one master can attempt to control the bus at the same

time without corrupting the message. The system is not dependent on

any single master.

Arbitration Procedure to ensure that, if more than one master simultaneously tries

to control the bus, only one is allowed to do so and the message is not

corrupted. The device that loses arbitration becomes the slave of the

device that wins.

Synchronization Procedure to synchronize the clock signals of two or more devices

MCU 1

Display

Serial memory

MCU 2

Data line (SDA)

Clock line (SCL)

Contents

Main Page Page Contents Page Page Page Page Page List of Tables Page List of Figures Page Page Page Page About This Manual Using This Manual Text Conventions Register Conventions Related Documents 1 General Description 1.1 MN102H Series Overview 1.2 MN102H Series Fea tures Page Page 1.3 MN102H Series Des cription Page Page Page MN102H Series Description ( 7 machine cycles Max. 6 machine cycles Interrupt 25 1.4 General Sp ecifications Table 1-1 General Specifications Parameter Specification General Specifications 27 Table 1-1 General Specifications Parameter Specification 28 1.5 Block Diagram Figure 1-8 Functional Block Diagram 29 Table 1-2 Block Diagram Explanation Block Description 30 1.6 Pin Descriptions 1.6.1 MN102H85K Pin Description 64-Pin SDIP Top View 31 1.6.2 MN102H75K Pin Description 84-Pin QFP Top View 32 Table 1-3 Pin Functions Block Pin Name I/O Pin Count Description 33 Table 1-3 Pin Functions (Continued) Block Pin Name I/O Pin Count Description Page Bus Interface 35 1.7 Bus Interface 1.7.1 Description Figure 1-15 Memory Space in External Extension Mode External Expansion Mode 1.7.2 Bus Interface Control Registers 2 Interrupts 2.1 Description 38 Figure 2-2 Interrupt Vector Group and Class Assignments 39 Figure 2-3 Interrupt Servicing Time Table 2-2 Handler Preprocessing Sequence Assembler Bytes Cycles Table 2-3 Handler Postprocessing Sequence Assembler Bytes Cycles Program 2.2 Interrupt Setup Examples 2.2.1 Setting Up an External Pin Interrupt Page 2.2.2 Setting Up a Watchdog Timer Interrupt Page 2.3 Interrupt Control Registers Page Interrupt Control Registers 46 Table 2-4 Interrupt Control Registers Register Address R/W Description Interrupt Control Registers 47 Table 2-4 Interrupt Control Registers Register Address R/W Description Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3 Low-Power Modes 3.1 CPU Modes 3.1.1 Description 3.1.2 Exiting from SLOW Mode to NORMAL Mode 3.1.3 Notes on Invoking and Exiting STOP and HALT Modes Low-Power Modes Turning Individual Functions On and Off 75 3.2 Turning Individual Functions On and Off 3.3 CPU Control Register 8-Bit Timer Description 77 4Timers TM3UDIR TM0O TM3 B 4.2 8-Bit Timer Features Table 4-1 8-Bit Timer Functions and Features Function/Feature Timer 0 Timer 1 Timer 2 Timer 3 8-Bit Timer Block Diagrams 79 4.3 8-Bit Timer Block Diagrams Reload Figure 4-3 Timer 0 Block Diagram Figure 4-4 Timer 1 Block Diagram 8-Bit Timer Block Diagrams 80 Figure 4-5 Timer 2 Block Diagram Figure 4-6 Timer 3 Block Diagram 4.4 8-Bit Timer Timing 4.5 8-Bit Timer Setup Examples 4.5.1 Setting Up an Event Counter Using Timer 0 83 TM0UDICL (example) x00FC74 TM0UDICH (example) x00FC75 TM0BR (example) x00FE 10 Figure 4-10 Event Counter Timing (Timer 0) 4.5.2 Setting Up an Interval Timer Using Timers 1 and 2 85 TM2UDICH (example) x00FC71 TM1MD (example) x00FE21 TM2UDICL (example) x00FC70 TM1UDICH (example) x00FC73 86 TM2MD (example) x00FE22 Figure 4-13 Interval Timer Timing (Timers 1 and 2) 8-Bit Timer Control Registers 87 4.6 8-Bit Timer Control Registers TM0BCTM3BC: Timer n Binar y Counter x00FE00x00FE03 TM0BRTM3BR: Timer n Base Register x00FE10x00FE13 TM0MDTM3MD: Timer n Mode Register x00FE20x00FE23 TMnEN: TMnBC count enable 4.7 16-Bit Timer Description 16-Bit Timer Features 89 4.8 16-Bit Timer Features Table 4-3 16-Bit Timer Functions and Features Function/Feature Timer 4 Timer 5 16-Bit Timer Block Diagrams 90 4.9 16-Bit Timer Block Diagrams CB Time 4.10 16-Bit Timer Timing Figure 4-15 Timer 4 Block Diagram Page Page Page 4.11 16-Bit Timer Setup Examples 4.11.1 Setting Up an Event Counter Using Timer 4 Page 4.11.2 Setting Up a Single-Phase PWM Output Signal Using Timer 4 Page Page 16-Bit Timer Setup Examples 99 Figure 4-30 Single-Phase PWM Output Timing (Timer 4) Page 4.11.3 Setting Up a Two-Phase PWM Output Signal Using Timer 4 16-Bit Timer Setup Examples 102 P2DIR (example) x00FFE2 TM0BR (example) x00FE 10 Page Page Page 4.11.4 Setting Up a Single-Phase Capture Input Using Timer 4 Page 4.11.5 Setting Up a Two-Phase Capture Input Using Timer 4 Page Page 4.11.6 Setting Up a 4x Two-Phase Encoder Input Using Timer 5 As figure 4-41 shows, you can set different values for A and B interrupts. (TM5LP must be 0.) Page Page 4.11.7 Setting Up a 1x Two-Phase Encoder Input Using Ti mer 5 As figure 4-45 shows, you can set different values for A and B interrupts. (TM5LP must be 0.) Page Page 4.11.8 Setting Up a One-Shot Pulse Output Using Timer 5 In this example, timer 5 outputs a one-shot pulse. The pulse width is two clock cycles. Page Page 4.11.9 Setting Up an External Count Direction Controller Using Timer 5 Page Page 4.11.10Setting Up External Reset Control U sing Timer 5 In this example, timer 5 is reset by an external signal while counting up. Page 16-Bit Timer Control Registers 125 4.12 16-Bit Timer Control Registers TM4CB/TM5CB: Timer n Compare/Capture Register B x00FE88/x00FE98 TM4BC/TM5BC: Timer n Binary Counter x00FE82/x00FE92 TMnCA and TMnCB are 16-bit access registers. Use the MOV instruction to write to them. TM4CA/TM5CA: Timer n Compare/Capture Register A x00FE84/x00FE94 Page 127 5 Serial Interfaces Figure 5-1 Serial Interface Configuration Example 5.1 Description 5.2 Features Connecting the Serial Interfaces 5.3 Connecting the Serial Interfaces Figures 5-2, 5-3, and 5-4 illustrate six different methods of connecting the serial interface. 5.3.1 Synchronous Serial Mode Connections 5.3.2 UART Mode Connections Figure 5-3 shows serial port connections for either simplex or full-duplex UART transfers. 5.4 UART Mode Baud Rates In these timing charts, the character length is 8 bits and there is parity. 5.5 Serial Inte rface Timing 5.5.1 Synchronous Serial Mode Timing 5.5.2 UART Mode Timing 5.6 Serial Inte rface Setup Example s 5.6.1 Setting Up UART Transmission Using Serial Interface 0 Page Page 5.6.2 Setting Up Synchronous Serial Reception Using Serial Interface 0 5.6.3 Setting Up the Serial Interface Clock Page 5.6.4 Setting Up I2C Transmission Using Serial Interface 0 Page 5.6.5 Setting Up I2C Reception Using Serial In terface 0 5.7 Serial Interf ace Control Registers Page Page 143 6 Analog-to-Digital Converter Figure 6-1 ADC Architecture 6.1 Description 6.2 Features M U X 6.3 Block Diagram 6.4 A/D Conversion Timing 6.4.1 Selecting the ADC Clock Source Figure 6-2 ADC Block Diagram Figure 6-3 ADC Timing 6.4.2 Single Channel/Single Conversion Timing 6.4.3 Multiple Channel/Single Conversion Timing 6.4.4 Single Channel/Continuous Conversion Timing 6.4.5 Multiple Channel/Continuous Conversion Timing 6.5 ADC Setup Examples 6.5.1 Setting Up Software-Controlled Single-Channel A/D Conversion 6.5.2 Setting Up Hardware-Controlled Intermittent Three-Channel A/D Conversion Page 6.6 ADC Control Registers These buffers hold the 8-bit A/D conversion data. Their value is unknown after reset. Page 6.7 Cautions about Analog-to-Digital Converter 153 7 On-Screen Display 7.1 Description 7.2 Features Table 7-1 OSD Functions and Features Function/Feature Text Layer Graphics Layer In closed-caption mode: 7.3 Block Diagram Polarity switch Figure 7-1 OSD Block Diagram Clock select 7.4 Power-Saving Considerations in the OSD Block 7.5 OSD Operation 7.5.1 OSD Clock 7.5.2 External Input Sync Signals 7.5.3 Multi-Layer Format 7.5.4 Output Pin Setup 7.5.5 Microcontroller Interface 7.5.6 VRAM 7.5.7 Conditions for VRAM Writes 7.6 Standard and Extended Display Modes 7.6.1 Cursor Layer Display Modes 7.6.2 Graphics Layer Display Modes 161 7.7 Display Setup Examples 7.7.1 Setting Up the Graphics Layer Table 7-5 Example Graphics VRAM Settings Line No. RAM Addr. RAM Data Data Type Description 162 Figure 7-4 Graphics Display Example 163 7.7.2 Setting Up the Text Layer Table 7-6 Example Text VRAM Settings Line No. RAM Addr. RAM Data Data Type Description 164 Figure 7-5 Text Display Example 165 7.8 VRAM 7.8.1 VRAM Operation CC: Character Code ID Code: 00 CCH[9:0] Specifies the address of one of 1024 characters stored in the ROM. COL: Color Control Code (Normal Mode) ID Code: 10 BSHAD[1:0] Page Page Page 169 7.8.2 VRAM Organization Text RAM Addresses Graphics RAM Addresses Program Data and Stack Area Graphics VRAM Text VRAM 170 A. GEXTE = 1 B. GEXTE = 0 Figure 7-7 Graphics VRAM Organization for Two Modes 7.8.3 Cautions about the number of display code set to VRAM 172 7.9 ROM 7.9.1 ROM Organization Text ROM Addresses Each character requires 36 bytes. Program Data Area 7.9.2 Graphics ROM Organization in Different Color Modes Line 16 Use graphics palette 6 Use graphics palette 5 Use graphics palette 4 Graphic Tile Codes 8 colors 96 bytes 4 colors 64 bytes Graphic Tile Codes 8 colors 108 bytes 4 colors 72 bytes 176 Line 16 data 8 bytes 32 bytes Line 16 data 2 bytes Line 16 data 4 bytes 177 Line 18 data 8 bytes 36 bytes Line 18 data 2 bytes Line 18 data 4 bytes 7.10 Setting Up t he OSD 7.10.1 Setting Up the OSD Display Colors Page Page Page Setting Up the OSD 182 Figure 7-21 OSD Signal Waveform Setting Up the OSD Internal DAC To pins Analog output YS 183 7.10.2 Text Layer Functions Page Page 7.10.3 Display Sizes Page 7.10.4 Setting Up the OSD Display Position Page 7.11 DMA and Interrupt Timing DMA and Interrupt Timing 192 Figure 7-30 DMA and Interrupt Timing for the OSD 7.12 Selecting the OSD Dot Clock 7.13 Controlling the Shuttering Effect 7.13.1 Controlling the Shuttered Area Controlling the Shuttering Effect 195 Figure 7-31 Shuttered Area Setup Examples 7.13.2 Controlling Shutter Movement Controlling the Shuttering Effect 197 Figure 7-32 Shutter Movement Setup Examples 7.13.3 Controlling Shuttering Effects ABCDE CDE ABCDE 7.13.4 Controlling Line Shuttering ABCDE 7.14 Field Detection Circuit 7.14.1 Block Diagram 7.14.2 Description 7.14.3 Considerations for Interlaced Displays 203 7.15 OSD Registers A17 A8 All registers in OSD block cannot be written by byte (by word only). Read by byte is possible. CROMEND: Text ROM End Address Register x007F00 GROMEND: Graphics ROM End Address Register x007F02 Page 0: Graphics color palette 1 1: Graphics color palette 2 Use the same ROM data as that used for the graphics. Page Page Page Page Page Page Page 213 CPT0CPTF: Text Palette Colors 015 Registers x007F80x007F9E 214 BBSHD: Black Box Shadowing Register x007FA4 Page 8 IR Remote Signal Receiver 8.1 Description 217 8.2 Block Diagram Figure 8-1 IR Remote Signal Receiver Block Diagram 8.3 IR Remote Signal Receiver Operation 8.3.1 Operating Modes 8.3.2 Noise Filter 8.3.3 8-Bit Data Reception IR Remote Signal Receiver Operation 220 8.3.4 Identifying the Data Format 5-/6-bit format HEAMA format HEAMA format < 6 TS cycles 6 TS cycles 5-/6-bit format < 12 TS cycles 12 TS cycles Table 8-2 Long and Short Data Identification Operating Mode Long Data Short Data HEAMA format 10 TS cycles < 2 TS cycles 5-/6-bit format 20 TS cycles < 4 TS cycles 8.3.5 Generating Interrupts 8.3.6 Controlling the SLOW Mode 8.4 IR Remote Signal Receiver Control Regis- ters Page Page Page 9 Closed-Caption Decoder 9.1 Description 9.2 Block Diagram 228 9.3 Functional Description CLH VREFLS 1 F (Used as P33) 9.3.2 Clamping Circuit A/D This block clamps the input video signal (CVBS0, CVBS1). Table 9-2 Caption decoder register setting VBI control ADC control Clamp control Figure 9-5 Clamping Circuit 9.3.3 Sync Separator Circuit 231 Figure 9-6 Sync Separator Circuit Block Diagram Page 9.3.4 Data Slicer 9.3.5 Controller and Sampling Circuit Page 236 9.4 Closed-Caption Decoder Registers Address CCD1 Table 9-9 Closed-Caption Decoder Register Register CCD0 Address R/W Description Page Page 239 HNUM: HSYNC Count Register x007E06 (HNUMW x007E26) VBIIRQ[4:0]: VBI interrupt timing control SBFLAG: Start bit detection fla g 0: No start bit detected 1: Start bit detected HNUM[4:0]: HSYNC count during the VBI interval This field indicates the H line number, from 0 to 25. For designs using the closed-cap- tion decoder, always tie the ACQ1 register to x1312. ACQ1: ACQ Capture Timing Control Register 1 x007E08 (ACQ1W x007E28) This field indicates the width, in clock units, from the second to the third CRI1FQW[7:0]: CRI frequency width 1 This field indicates the width, in clock units, from the first to the second CRIFB: CRI Frequency Width Register B x007E0E (CRIFBW x007E2E) CRI4FQW[7:0]: CRI frequency width 4 Set this field so that the last CRI rising edge is included. The valid range is x000 to x7FF. DATAS: Data Capture Start Timing Control Register x007E18 (DATASW x007E38) DATAS[10:0]: Start position for data capture 242 DATAE: Data Capture Stop Timing Control Register x007E1A (DATAEW x007E3A) 0: Low-pass filter 1 1: Low-pass filter 2, 3, or 4 (set in NFSW[1:0]) NFSW[1:0]: Noise filter switch (for composite sync separator) 243 FQSEL: Frequency Select Register x007EC2 (FQSELW x007EE2) VFQDIV[5:0]: Sampling frequency setting for VSYNC separator In this field, set the ratio by which to divide the sampling frequency for the HSYNC separator. FQDIV[3:0]: Sampling frequency setting for HSYNC separator In this field, set the ratio by which to divide the A/D sampling frequency. SCMING: Minimum Sync Level Detection Interval Set Register x007EC4 (SCMINGW x007EE4) SCMING[9:0]: Interval setting for the minimum sync level detection Page Page 246 HSEP1: HSYNC Separator Control Register 1 x007ECE (HSEP1W x007EEE) HSFREQ[10:0]: Correction HSYNC frequency HSEP2: HSYNC Separator Control Register 2 x007ED0 (HSEP2E x007EF0) 0: Odd field 1: Even field VPHASE[9:0]: Phase difference setting for VSYNC and HSYNC HLOCKLV: Sync Separator Detection Control Register 1 x007ED4 (HLOCKLVW x007EF4) HLOCKLV[8:0]: Sync separator detection threshold 0: 0H to 127H VSYNC separation mask 1: No mask Use this register to monitor the status of the sync separator. 0: Asynchronous 1: Synchronous Page 10 Pulse Width Modulator 10.1 Description Pulse Width Modulator 10.2 Block Diagram 10.3 PWM Data Registers 11 I/O Ports 11.1 Description 11.2 I/O Port Circuit Diagrams Page Page Page Page 257 Figure 11-6 /PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2) 258 Figure 11-7 P24/TM4IC/SBT1 (Port 2) To use as SBT1,set P2MD8 and P2MD9 to 0. Page 260 Figure 11-9 P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port 3), and P40/DAYMOUT/YM (Port 4) 261 Figure 11-10 P25/TM4IOB/SBI1/SBD1 and P26/TM4IOA/SBO1 (Port 2) 262 Figure 11-11 P55 and P56 (Port 5) Page 264 Figure 11-13 P02/SCL1 (Port 0) and P61/SCL0 (Port 6) 265 Figure 11-14 P01/SDA1 (Port 1) and P60/SDA0 (Port 6) Page Page Page 269 Figure 11-18 P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4) Figure 11-19 P44/TM5IC/HI1 (Port 4) 270 Figure 11-20 P45/OSDXO and P46/OSDXI (Port 4) Page Page Page Page Page Page 11.3 I/O Port Control Registers Page Page Page Page Page Page Page Page Page Page 12 ROM Correction 12.1 Description Main Start 12.2 Block Diagram 12.3 Programming Considerations 12.4 ROM Correction Control Registers Page ROM Correction AMCHIHn is an 8-bit access register. AMCHILn is a 16-bit access register. CHDATn is an 8-bit access register. 13 I2C Bus Controller 13.1 Description Page 295 Slave A. Master Transmitter B. Master Receiver C. Slave Transmitter 13.2 Block Diagram I2C sequence controller 13.3 Functional Description Figure 13-4 I2C Bus Controller Block Diagram Table 13-3 Control Registers for Clamping Circuit Register Page Address Description Page Setting Up the I2C Bus Connection 298 13.4 Setting Up t he I2C Bus Connection I Figure 13-5 Pin Control Circuit for the I2C Bus Controller C Circuit SDA and SCL Waveform Characteristics 13.5 SDA and SCL Waveform Characteristics Figure 13-6 SDA and SCL Waveforms Table 13-5 SDA and SCL Waveform Characteristics Parameter Symbol Min Max Unit 13.6 I2C Interface Setup Examples 13.6.1 Setting Up a Transition from Master Transmitter to Mas- ter Receiver Page 13.6.2 Setting Up a Transition from Slave Receiver to Slave Transmitter Page 13.7 I2C Bus Interface Registers Page Page H Counter 307 14 H Counter Figure 14-2 provides a schematic diagram of an example counter operation. 14.1 Description 14.2 Block Diagram 14.3 H Counter Operation Page Page 14.4 H Counter Control Registers H Counter This field stores the HI0 clock source count. It becomes x3FF on over- flow. This field stores the HI1 clock source count. It becomes x3FF on over- flow. 312 Appendix ARegister Map 313 Table A-2 Register Map: x00FC00 to x00FDFF 20 314 Table A-3 Register Map: x00FE00 to x00FFFF 20 Page Appendix BMN102HF75K Flash EEPROM Version B.1 Description MN102HF75K Flash EEPROM Version Benefits 317 B.2 Benefits B.3 Using the PROM Writer Mode Figure B-2 PROM Writer Hardware Setup Figure B-3 Pin Configuration for Socket Adaptor MN102HF75K Flash EEPROM Version Using the PROM Writer Mode 318 Table B-2 PROM Writer Hardware Hardware Part Device MN102HF75KBF MN102HF85KDP B.4 Using the Onboard Serial Programming Mode B.4.1 Configuring the System for Onboard Serial Programming B.4.2 Circuit Requirements fo r the Target Board B.4.3 Microcontroller Hardware Used in O nboard Serial Pro- gramming B.4.4 Microcontroller Memory Map Used Du ring Onboard Serial Programming B.4.5 Microcontroller Clock on the Target Board B.4.6 Setting Up the Onboard Serial Progra mming Mode Page B.4.7 Branching to the User Program B.5 Reprogramming Flow B.6 Programming Times MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.1.0 to 1.1) Using This Manual P16 Using This Manual P17 MN10200 Series Linear Addressing High-Speed Version LSI User Manual P17 MN102H Series LSI User Manual P24 P27 P27 2 P30 1.6 Pin Descriptions I/O ports Figure 1-9 MN102H75K Pin Configuration in Single-Chip Mode 1.6.1 MN102H85K Pin Description P33 P37 P72 3.1 CPU Modes P72 Page Page Page Page Semiconductor Company, Matsushita Electric Industrial Co., Ltd. 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