ROM Correction
ROM Correction Control Registers
Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual
290
Panasonic
12.4 ROM Correction Control Registers
Table 12-1 shows the organization of the address match and data registers for
ROM correction. Write a ROM address to be corrected to an AMCHIHn and
AMCHILn register pair and write the corrected data to the associated CHDATn
register. Enable ROM correction for the associated address in the ROMCEN
register.
ROMCEN: ROM Correction Enable Register x’00FCF0’
ROMCEN15: Address 15 ROM correction enable
0: Disable
1: Enable
ROMCEN14: Address 14 ROM correction enable
0: Disable
1: Enable
ROMCEN13: Address 13 ROM correction enable
0: Disable
1: Enable
Table 12-1 ROM Correction Address Match and Data Registers
ROM Address Address Match Register Data Register
High Order Low Order
Address 0 AMCHIH0 x’00FD02’ AMCHIL0 x’00FD00’ CHDAT0 x’00FD40’
Address 1 AMCHIH1 x’00FD06’ AMCHIL1 x’00FD04’ CHDAT1 x’00FD44’
Address 2 AMCHIH2 x’00FD0A’ AMCHIL2 x’00FD08’ CHDAT2 x’00FD48’
Address 3 AMCHIH3 x’00FD0E’ AMCHIL3 x’00FD0C’ CHDAT3 x’00FD4C’
Address 4 AMCHIH4 x’00FD12’ AMCHIL4 x’00FD10’ CHDAT4 x’00FD50’
Address 5 AMCHIH5 x’00FD16’ AMCHIL5 x’00FD14’ CHDAT5 x’00FD54’
Address 6 AMCHIH6 x’00FD1A’ AMCHIL6 x’00FD18’ CHDAT6 x’00FD58’
Address 7 AMCHIH7 x’00FD1E’ AMCHIL7 x’00FD1C’ CHDAT7 x’00FD5C’
Address 8 AMCHIH8 x’00FD22’ AMCHIL8 x’00FD20’ CHDAT8 x’00FD60’
Address 9 AMCHIH9 x’00FD26’ AMCHIL9 x’00FD24’ CHDAT9 x’00FD64’
Address 10 AMCHIHA x’00FD2A’ AMCHILA x’00FD28’ CHDAT10 x’00FD68’
Address 11 AMCHIHB x’00FD2E’ AMCHILB x’00FD2C’ CHDAT11 x’00FD6C’
Address 12 AMCHIHC x’00FD32’ AMCHILC x’00FD30’ CHDAT12 x’00FD70’
Address 13 AMCHIHD x’00FD36’ AMCHILD x’00FD34’ CHDAT13 x’00FD74’
Address 14 AMCHIHE x’00FD3A’ AMCHILE x’00FD38’ CHDAT14 x’00FD78’
Address 15 AMCHIHF x’00FD3E’ AMCHILF x’00FD3C’ CHDAT15 x’00FD7C’
Note: All registers reset to 0.
Bit:1514131211109876543210
ROMC
EN15 ROMC
EN14 ROMC
EN13 ROMC
EN12 ROMC
EN11 ROMC
EN10 ROMC
EN9 ROMC
EN8 ROMC
EN7 ROMC
EN6 ROMC
EN5 ROMC
EN4 ROMC
EN3 ROMC
EN2 ROMC
EN1 ROMC
EN0
Reset:0000000000000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W