10
80
8050QMA
50QMA N/B Maintenance
N/B Maintenance
•Intel®Dothan processor
•AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for reduced
power)
•Supports 32-bit AGTL+ host bus addressing
•Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz)
•2X Address, 4X data
•Host bus dynamic bus inversion HDINV support
•12 deep, in-order queue
Memory System
•Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide.
•Supports SO-DIMMs of the same type (e.g.,all DDR or all DDR2), not mixed.
•Maximum of two, double-sided unbufferedSO-DIMMs (4 rows populated)
•Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 rows = 128 MB) using
256-MB technology
•Maximum amount of memory supported is 2 GB using 1-GB technology.
MiTac Secret
Confidential Document