National Instruments NI 5401 - page 6

Contents

NI 5401 User Manual vi www.natinst.com

SYNC Output and Duty Cycle........................................................................2-9

Output Attenuation..........................................................................................2-9

Output Impedance...........................................................................................2-10

Output Enable.................................................................................................2-10

Pre-Attenuation Offset....................................................................................2-11

Phase-Locked Loops and Board Synchronization.........................................................2-11

Analog Filter Correction................................................................................................2-13

RTSI/PXI Trigger Lines................................................................................................2-14

Calibration.....................................................................................................................2-15

Appendix A

Specifications

Appendix B

Optional Accessories

Appendix C

Frequency Resolution and Lookup Memory

Appendix D

Technical Support Resources

Glossary

Index

Figures

Figure 1-1. NI 5401 I/O Connectors........................................................................ 1-2

Figure 1-2. Output Levels and Load Termination Using a

50 Ω Output Impedance........................................................................1-3

Figure 1-3. SYNC Output and Duty Cycle..............................................................1-4

Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments............................ 1-5

Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments.................................... 1-7

Figure 1-6. VirtualBench-FG Soft Front Panel for Function Generation................1-11

Figure 1-7. VirtualBench-FG General Settings Dialog Box for the NI 5401..........1-12

Figure 1-8. VirtualBench-FG Signals Settings Dialog Box for the NI 5401...........1-12

Figure 1-9. VirtualBench-FG Load Waveform Dialog Box....................................1-13

Figure 1-10. VirtualBench-FG Frequency List Editor Dialog Box...........................1-14

Figure 1-11. Waveform Editor Soft Front Panel....................................................... 1-15

Contents

Main Page Important Information Warranty Copyright Trademarks WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS Conventions Contents Chapter 1 Generating Functions with the NI 5401 Chapter 2 Function Generator Operation Page Table Generating Functions with the NI 5401 About Your NI 5401 Connecting Signals ARB Connector SYNC Connector PLL Ref Connector Chapter 1 Generating Functions with the NI5401 National Instruments Corporation 1-5 NI 5401 User Manual Pattern Out Connector (PCI Only) This connector is used on the NI 5401 for PCI to supply the external trigger input to the board. Figure 1-4. NI 5401 50-Pin Digital Connector Pin Assignments Connector Pin Assignments Signal Descriptions SHC50-68 50-Pin Cable Connector Chapter 1 Generating Functions with the NI5401 Figure 1-5. SHC50-68 68-Pin Connector Pin Assignments National Instruments Corporation 1-7 NI 5401 User Manual Software Options for Your NI 5401 Software Included with Your NI 5401 VirtualBench VirtualBench-FG Waveform Editor NI-FGEN Instrument Driver Additional National Instruments Development Tools LabVIEW LabWindows/CVI ComponentWorks Using the Soft Front Panels to Generate Waveforms Generating Standard Functions Page Generating Multiple Frequencies in a Sequence Page Waveform Editor Power-Up and Reset Conditions National Instruments Corporation 2-1 NI 5401 User Manual Function Generator Operation This chapter describes how to use your NI 5401. Figure2 -1 shows the NI 5401 block diagram. Figure 2-1. NI5401 Block Diagram Generating Waveforms Direct Digital Synthesis (DDS) Frequency Hopping and Sweeping Triggering Trigger Sources Modes of Operation Single Trigger Mode Continuous Trigger Mode Stepped Trigger Mode Analog Output NI 5401 User Manual 2-8 www.natinst.com Figure2 -8 shows the essential block diagram of analog waveform generation. Figure 2-8. Analog Output and SYNC Out Block Diagram SYNC Output and Duty Cycle Output Attenuation Output Impedance Output Enable Pre-Attenuation Offset Phase-Locked Loops and Board Synchronization NI 5401 User Manual 2-12 www.natinst.com Figure 2-11. PLL Architecture for the NI5401 for PCI Figure 2-12. PLL Architecture for the NI5401 for PXI Caution Do not increase the voltage level of the clock signal at the PLL reference input clock, they are frequency locked, but the phase relationship is indeterminate. connector by more than the specified limit, 5 Vpk-pk. Note If two or more NI5401 devices are locked to each other using the same reference Analog Filter Correction NI 5401 User Manual 2-14 www.natinst.com RTSI/PXI Trigger Lines Figure 2-14. RTSI Trigger Lines and Routing for the NI5401 for PCI Figure2 -15 shows the PXI trigger lines and routing of NI5401 for PXI signals to the RTSI switch. Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and Routing for the NI5401 for PXI Calibration A Specifications Analog Output Voltage Output Sine Spectral Purity Filter Characteristics Page SYNC Out External Clock Reference Input Internal Clock Mechanical B Optional Accessories Cabling C Frequency Resolution and Lookup Memory Page D Technical Support Resources NI Web Support On-Line Problem-Solving and Diagnostic Resources Software-Related Resources Worldwide Support Glossary Numbers/Symbols A B C D E F G H I K L M N O P R S T U V W Index A B C D I L M N O R S T V W