National Instruments PCI-6023E, PCI-6024E, PCI-6025E - page 77

Chapter 4 Signal Connections
PCI-6023E/6024E/6025E User Manual 4-48
© National Instruments Corporation
leave the DIO7 pin free for general use. Figure 4-41 shows the timing
requirements for the GATE and SOURCE input signals and the timing
specifications for the OUT output signals of your board.
Figure 4-41. GPCTR Timing Summary
The GATE and OUT signal transitions shown in Figure4-41 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
diagram, but with the source signal inverted andreferenced to the falling
edge of the source signal, would apply when the counter is programmed to
count falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on your board.
Figure 4-41 shows the GATE signal referenced to the rising edge of a
source signal. The gate must be valid (either high or low) for at least 10 ns
before the rising or falling edge of a source signal for the gate to take effect
at that source edge, as shown by tgsu and tgh in Figure 4-41. The gate signal
is not required to be held after the active edge of the source signal.
If you use an internal timebase clock, the gate signal cannot be
synchronized with the clock. In this case, gates applied close to a source
edge take effect either on that source edge or on the next one. This
SOURCE VIH
VIL
VIH
VIL
tsc tsp
tgsu tgh
tgw
GATE
tout
OUT VOH
VOL
sc
t
t
t
t
t
t 50 ns minimum
sp 23 ns minimum
gsu 10 ns minimum
gh 0 ns minimum
gw 10 ns minimum
out 80 ns maximum
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
tsp
PCI.book Page 48 Wednesday, September 16, 1998 9:09 AM