NEC 5800/1000 manual Features for performance improvement, Compiler

Supercomputer-class Performance

Features for performance improvement

Dual-Core Intel® Itanium® processor and high-speed inter/intra Cell cache-to-cache data transfer

At the heart of the Express5800/1000 series server is the 64-bit Dual-Core Intel® Itanium® processor, redesigned for even faster processing of larger data sets.

The system has been equipped with the NEC designed chipset, “A3 ”, in order to improve performance by utilizing, to its full extent, the massive 24MB of cache memory that has been built into the Dual-Core Intel® Itanium® processor

Technologies to increase cache-to-cache data transfer, such as the VLC architecture and CCI, have been implemented

to maximize the performance for enterprise mission critical[1080Rf] computing.

Increased Memory Bandwidth

Improved Inter/Intra-Cell memory data transfer

Very Large Cache (VLC) Architecture

High-speed/low latency Intra-Cell cache-to-cache data transfer

Dedicated Cache Coherency Interface (CCI)

High-speed/low latency Inter-Cell cache-to-cache data transfer

Crossbar-less configuration

Improved data transfer latency between Cell/Cell and Cell/IO

[1320Xf]

[1160Xf]

High processing power of the Dual-Core Intel® Itanium® processor

Dual-Core, massive L3 cache and EPIC (Explicitly Parallel Instruction Computing) architecture

The Dual-Core Intel® Itanium® processor is Intel’s first production in the Itanium® processor family with two complete 64-bit cores on one processor and also the first member of the Intel® Itanium® processor family to include Hyper-Threading Technology, which provides four times the number of application threads provided by earlier single-core implementations.

With a maximum of 24MB of On-Die L3 cache, the Dual-Core Intel®

Itanium® processor excels at high volume data transactions.

EPIC architecture provides a variety of advanced implementations of parallelism, predication, and speculation, resulting in superior Instruction-Level Parallelism (ILP) to help address the current and future requirements of high-end enterprise and technical workloads.

Conventional Superscalar RISC Processor

Parallel processing with EPIC architecture

Original Source Code

Compiler

Sequential

Machine Code

Some level of parallelization is achieved however, it is not maximized nor efficient

Partial HW

Parallelization

Original Source Code

Intel® Itanium® processor supported compiler

Intel® Itanium® processor
source is parallelized at
compile time
Efficient parallel processing
is made possible due to the
thorough parallelization.	Hardware

In the EPIC architecture, parallelization is run at compile time, allowing for maximum parallelization with minimal scheduling.

4