NEC 1320Xf/1160Xf n Internal Connections of the, n System Hardware Layout of the Express5800/1000

Models: 5800 Series 1000 Series 1320Xf/1160Xf 1080Rf

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n Internal Connections of the

n Internal Connections of the

n System Hardware Layout of the Express5800/1000

Express5800/1000 Series

Series Server (1320Xf)

 

 

 

Direct data transfer of large cache data

Increased inter-Cell data transfer speeds

Cell

(CCI)

 

Cell

Cell

Coherency Interface

Cell

 

Cell

Cache

 

Cell

Cell

Processor

 

 

Processor

Cell Controller

 

 

Processor

 

A3 Chipset

 

 

 

Processor

 

 

 

 

Memory

Memory

High-speed crossbar

Service

Processor *1

Clock card *1

HDD Bay

Power

Distribution

Unit (PDU)

n System Hardware Layout of the Express5800/1000 Service Processor

Express5800/1000 Series Clock card

Series Server (1320Xf) HDD Bay

Cell Power Distribution Unit

A3 Chipset Power Bay

Fan box

Cell card

* Redundant configuration available

Fan box

PCI box

*Redundant configuration available

Power Bay

Mainframe-class RAS features Fan box

Reliability / Availability Cell card

•Dual-Core Intel® Itanium® processor: PCI box

•Enhanced error detection of the high-speed interconnect: Crossbar card

Serviceability PCI slots

Crossbar

card

PCI slots

Hot Pluggable *2

FullyN+1

Redundant Redundant

*1 Redundancy is optional

*2 Ability to replace a failed component without shutting down other partitions

Mainframe-class RAS features

Reliability / Availability
Dual-Core Intel® Itanium® processor:

Error handling of hardware and operating system through Machine Check Architecture (MCA)

Memory mirroring: Continuous operation even in the event of a non-correctable error

Partial Chipset degradation: Avoid multi-partition shutdowns resulting from chipset failures

Highly Available Center Plane: System restoration after the replacement of a failed crossbar no longer requires a system shutdown

Complete modularization and redundancy: Improvements in fault resilience, continuous operation and serviceability

Clock modularization, redundancy and 16 processor domain segmentation: Minimizes downtime, and avoids multi partition shutdown due to clock failure

Diagnostics of the error detection circuits: Substantial strengthening of data integrity

Enhanced error detection of the high-speed interconnect:

Intricate error handling through multi bit error detection and retransmission of error data

Two independent power sources: Avoid system shutdown due to failures of the power distribution units

Serviceability

Autonomic reporting of logs with pinpoint prognosis of failed components allow for the realization of mainframe-class platform serviceability

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NEC 1320Xf/1160Xf n Internal Connections of the, n System Hardware Layout of the Express5800/1000, Express5800/1000 Series