Chapter 3 Register Setup of Each Function
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#define TM0BC (*(volatile unsigned char *)TM0BC_adr)
#define TM0OC_adr 0x3F52
#define TM0OC (*(volatile unsigned char *)TM0OC_adr)
#define TM0MD_adr 0x3F54
#define TM0MD (*(volatile unsigned char *)TM0MD_adr)
#define CK0MD_adr 0x3F56
#define CK0MD (*(volatile unsigned char *)CK0MD_adr)
/* Setting program*/
/* Operation is based on external signal, and prescaler is not set */
TM0OC = COUNT; /* Set timer value */
TM0MD = TM0CAS | TM0EN | TM0CK;
This sample is stored in the CD.
Stored directory: Sample\chapter3,4\Initial\ASM\TIMER\EVENT8\
Stored directory: Sample\chapter3,4\Initial\C\TIMER\EVENT8\
The timer pulse output can provide a pulse signal at an arbitrary frequency.
The period of the timer pulse output is twice as long as the period set on the compare register.
To provide timer pulse, set the output mode register (special register) of the port 1 to the timer output,
and set the input/output setting register to output. See "3.7.2 Port 1".)
The timer setting for timer pulse output setting is identical to that for the interval timer.
The PWM output generates the PWM basic component and provides it from the timer output pin when the
binary counter and the compare register of a timer match or on the overflow timing of the binary counter.
Since the PWM output uses the overflow of the binary counter, you can use only the frequency component
generated by the overflow of the timer. The resolution of the PWM output is fixed to the one 255th due to
the 8-bit counter.
The PWM output provides "1" until it counts up to the count set on the compare register after count start
(00), and then provides "0" until it overflows after the match to the compare register.
Since the frequency components use the timer overflow, they are determined by the prescaler setting. This
sample uses the low speed oscillation clock (assuming its oscillation is at 32.768 kHz) to set the 1/4 duty
output for the 128 Hz frequency.