Philips Semiconductors Product specification
PTN3501Maintenance and control device
2001 Jan 17 11
I2C-BUS TIMING CHARACTERISTICSSYMBOL PARAMETER MIN. TYP. MAX. UNIT
I2C-bus timing (see Figure 19; Note 1)
fSCL SCL clock frequency – – 400 kHz
tSW tolerable spike width on bus – – 50 ns
tBUF bus free time 1.3 – – µs
tSU;STA START condition set–up time 0.6 – – µs
tHD;STA START condition hold time 0.6 – – µs
trSCL and SDA rise time – – 0.3 µs
tfSCL and SDA fall time – – 0.3 µs
tSU;DAT data set–up time 250 – – ns
tHD;DAT data hold time 0 – – ns
tVD;DAT SCL LOW to data out valid – – 1.0 µs
tSU;STO STOP condition set–up time 0.6 – – µs
NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
handbook, full pagewidth
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO
tf
r
t
tBUF
tSU;STA 1 / f SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
SW00561
PROTOCOL
Figure 19.