Philips SCC2691 - page 16

Philips Semiconductors Product data sheet

SCC2691Universal asynchronous receiver/transmitter (UART)

2006 Aug 04 16

RDN

MPI

WRN

MPO

tPS tPH

tPD

SD00125

Figure 5. I/O Timing

WRN

INTERRUPT1

OUTPUT

RDN

INTERRUPT1

OUTPUT

VM

tIR

tIR

VOL +0.5V

VOL +0.5V

VOL

VOL

NOTES:

1. INTRN or MPO when used as interrupt outputs.

2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal,

VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment

are pronounced and can greatly affect the resultant measurement.

SD00126

Figure 6. Interrupt Timing

X1/CLK

C/T CLK

RxC

TxC

tCLK

tCTC

tRx

tTx

tCLK

tCTC

tRx

tTx

C1

C2

Y1

X1/CLK

X2

SCC2691

Y1 = 3.6864MHz, CL = 20pF

C1 = C2 = 24pF

CLK 5V

470Ω

X1

X2N/C

TYPICAL CRYSTAL SPECIFICATION

FREQUENCY. . . . . . . . . . . . . . 2–4MHz

LOAD CAPACITANCE (CL). . . 20 or 32pF (typical)

TYPE OF OPERATION . . . . . .PARALLEL RESONANT, FUND. MODE

DRIVING

FROM EXTERNAL

SOURCE

50k

to

150k

SD00127

Figure 7. Clock Timing

Contents

Main SCC2691Universal asynchronous receiver/transmitter (UART) DESCRIPTION FEATURES ORDERING INFORMATION Figure 2. Block Diagram COMMERCIAL INDUSTRIAL PACKAGES VCC = +5V +10%, TA = 0C to +70CVCC = +5V +10%, BLOCK DIAGRAM SD00123 PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARACTERISTICS SCC2691Universal asynchronous receiver/transmitter (UART) AC ELECTRICAL CHARACTERISTICS BLOCK DIAGRAM SCC2692, SCC68681 and SCC2698B Data Bus Buffer Extended baud rates for SCN2681, SCN68681, SCC2691, Interrupt Control Receiver and Transmitter RECEIVER FIFO Receiver Status Bits Receiver Reset and Disable SCC2691Universal asynchronous receiver/transmitter (UART) MULTI-PURPOSE INPUT PIN MULTI-PURPOSE OUTPUT PIN REGISTERS MR1 Mode Register 1 MR2 Mode Register 2 Table 2. Register Bit Formats MR2 (Mode Register 2) Channel Mode TxRTS Control CTS Enable Tx Stop Bit Length* CSR (Clock Select Register) Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B Table 2. Register Bit Formats (Continued) CTUR (Counter/Timer Upper Register) CSR Clock Select Register (see Table 6. also) Table 3. Baud Rate Selection Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B CR Command Register SR Channel Status Register ACR Auxiliary Control Register Table 4. ACR[6:4] Operating Mode Table 5. BRG Characteristics ISR Interrupt Status Register IMR Interrupt Mask Register CTUR and CTLR Counter/Timer Registers Page Page 2006 Aug 04 18 SD00128 Figure 11. Receiver Timing Figure 10. Transmitter Timing SD00129 The CTS, RTS, CTS Enable Tx signals Transmitter Disable Note Table 6. Baud Rates Extended Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B Receiver Reset in the Normal Mode (Receiver Enabled) Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11) Page Page Page Page yyyy mmm dd 25 Data sheet status Document status Product status[3] Definition Contact information Legal Information