1995 Mar 07 9
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
Gdiff(p-p) differential gain at nominal output
signals (peak-to-peak value) R−Y = 1.05 V (p-p) −−10 %
B−Y = 1.33 V (p-p) −−10 %
Y = 0.34 V (p-p) −−10 %
S/N signal-to-noise ratio nominal input; B =5 MHz;
note 2 50 −−dB
SVRR supply voltage ripple rejection note 3 30 −−dB
VODC output levels during clamping −5.3 −V
Synchronization channels
Gdiff gain difference (programmed value) −−10 %
B bandwidth −3dB −50 −MHz
+3 dB; gain×1−20 −MHz
±3 dB; gain×2−13 −MHz
Vi(p-p) input amplitude of sync signal for
correct operation of clamp pulse
generator (peak-to-peak value)
0.2 −2.5 V
|Z23-22|output impedance (pin 23) −20 30 Ω
Vo(p-p) maximum undistorted output
amplitude (pin 23)
(peak-to-peak value)
2.5 −−V
V
ODC output level on top of sync pulse 1.5 1.9 2.4 V
I2C-bus inputs for SDA, SCL
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −1.5 V
IIH HIGH level input current −−10 µA
IIL LOW level input current −−10 µA
I2C-bus output for SDA (open collector)
VOL LOW level output voltage IOL =3mA −−0.4 V
Address selection inputs for S0, S1, S2
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −0.4 V
IIH HIGH level input current −010µA
I
IL LOW level input current −50 −10 0 µA
Fast switching input
VIH HIGH level input voltage 1 −3V
V
IL LOW level input voltage −0.3 −0.4 V
IIH HIGH level input current −0 500 µA
IIL LOW level input current −100 −−µA
t
sw switching time see Fig.5 −10 −ns
tdswitching delay see Fig.5 −20 −ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT