1999 Feb 16 8
Philips Semiconductors Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC) TDA8767Voltage controlled regulator input Vref (referenced to VCCA)
Vref(FS) full scale fixed voltage VCCA=5V −3.175 −V
Vi(p-p) −Vi(p-p) input voltage amplitude
(peak-to-peak value) differential mode −2.0 −V
single mode; Vi= 2.5 V −2.0 −V
Iref input current at Vref −10 −µA
Outputs (referenced to DGND)
DIGITAL OUTPUTS D11TO D0 AND IR (REFERENCED TO DGND)
VOL LOW-level output voltage IOL = 2 mA 0 −0.5 V
VOH HIGH-level output voltage IOH =−0.4 mA VCCO−0.5 −VCCD V
IOoutput current in 3-state 0.5 V < VO<V
CCO −20 −+20 µA
Switching characteristics
CLOCK FREQUENCY fclk (see Fig.3)
fclk(min) minimum clock frequency SH = HIGH −−1 MHz
SH = LOW −−1 kHz
fclk(max) maximum clock frequency
TDA8767H/1 10 −−MHz
TDA8767H/2 20 −−MHz
TDA8767H/3 30 −−MHz
tCPH clock pulse width HIGH 8.5 −−ns
tCPL clock pulse width LOW 8.5 −−ns
Analog signal processing; 50% clock duty factor; Vi−Vi= 2.0 V; Vref =V
CCA −2V;see Table1
LINEARITY
ILE integral non-linearity fclk = 4 MHz; ramp input −±3.0 ±4.0 LSB
DLE differential non-linearity fclk = 4 MHz; ramp input;
no missing codes
−±0.6 ±1 LSB
OFER offset error VCCA =V
CCD =V
CCO =5V;
T
amb =25°C; Vi=Vi; output
code = 2047
tbf −tbf LSB
GER gain error amplitude; spread
from device to device VCCA =V
CCD =V
CCO =5V;
T
amb =25°C;Vi−Vi=2.0 V tbf −tbf LSB
BANDWIDTH (fclk = 30 MHz); note 1
B analog bandwidth −1dB −9−MHz
−3dB −18 −MHz
tSTLH analog input settling time
LOW-to-HIGH transition full scale square wave;
note 3
−tbf −ns
tSTHL analog input settling time
HICH-to-LOW transition full scale square wave;
note 3
−tbf −ns
HARMONICS
THD total harmonic distortion fclk = 30 MHz; fi= 4.43 MHz;
note 2
−−64 −dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT