Philips UDA1334BT

2002 May 22 14

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334BT

14.3 Timing

VDDD =V

DDA= 1.8 to 3.6 V; Tamb =−20 to +85°C; RL=5kΩ;all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed; note 1.

Note

1. The typical value of the timing is specified at fs=44.1 kHz (sampling frequency).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing(see Fig.6)

Tsys system clock cycle time fsys = 256fs35 88 780 ns

fsys = 384fs23 59 520 ns

fsys = 512fs17 44 390 ns

tCWH system clock HIGH time fsys< 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

tCWL system clock LOW time fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

Reset timing

treset reset time 1 −−µs

Serial interface timing (see Fig.7)

fBCK bit clock frequency −−64fsHz

tBCKH bit clock HIGH time 50 −−ns

tBCKL bit clock LOW time 50 −−ns

trrise time −−20 ns

tffall time −−20 ns

tsu(DATAI) set-up time data input 20 −−ns

th(DATAI) hold time data input 0 −−ns

tsu(WS) set-up time word select 20 −−ns

th(WS) hold time word select 10 −−ns