2002 May 22 8
Philips Semiconductors Product specification
Low power audio DAC UDA1334BT
8.4 Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jittersensitivity is achieved. No post-filter is needed due to
theinherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.5 Power-on reset
The UDA1334BT has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 µs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
handbook, halfpage
VDDA
Vref(DAC)
3.0 V 13
12
MGU678
UDA1334BT
C1 >
10 µF
RESET
CIRCUIT
50 kΩ
50 kΩ
Fig.3 Power-on reset circuit.
handbook, halfpage
3.0
VDDD
(V)
1.5
0t
3.0
VDDA
(V)
1.5
0t
3.0
Vref(DAC)
(V)
1.5
1.25
0.75
0t
MGL984
>1 µs
Fig.4 Power-on reset timing.