Renesas M3A-HS60 Overview , 1.7 M3A-HS60 Memory Mapping

Overview

1.7 M3A-HS60 Memory Mapping

Rev.1.00 June 1,2005 1-8

REJ11J0002-0100Z

1

1.7 M3A-HS60 Memory Mapping

Figure1.7.1 shows the memory mapping example of SH7206 in the M3A-HS60.

Logical address Logical space of theSH7206 Memory Mapping of theM3A-HS60

H'0000 0000

H'003F FFFF CS0 space:64MB Flash Memory(4MB)

16-bit bus

User area

H'0400 0000

CS1 space:64MB User area

H'0800 0000

CS2 space:64MB User area

H'0C00 0000

H'0CFF FFFF CS3 space:64MB SDRAM(32MB)

32-bit bus

SDRAM(16MB)

16-bit bus

H'0DFF FFFF User area

User area

H'1000 0000

CS4 space:64MB User area

H'1400 0000

CS5 space:64MB User area

H'1800 0000

CS6 space:64MB Reserved area

(Disabled)

H'1C00 0000

CS7 space:64MB Reserved area

(Disabled)

H'2000 0000

CS0-CS7 spaces

(non-cacheable area) CS0-CS7 spaces

(non-cacheable area)

H'4000 0000

CS8 space:1GB User area

H'8000 0000

Reserved area

(Disabled) Reserved area

(Disabled)

H'FFF8 0000

Internal RAM(128KB) Internal RAM(128KB)

H'FFFA 0000

Internal RAM, Reserved Internal RAM, Reserved

H'FFFC 0000

H'FFFF FFFF Internal peripheral module Internal peripheral module

Note: There is the cacheable area from H’0000 0000~H’1FFF FFFF.

Figure1.7.1 Memory Mapping Example of SH7206

Contents

Main REJ11J0002-0100Z Issued:June 1,2005 Renesas32-Bit RISC Microcomputers SuperHTM RISC Engine Family/SH7200 Series/SH7206 Group M3 SH7206 CPU Board A -HS60 User's Manual Page Page Table of Contents Page Overview 1.1 Overview 1.2 Configuration Overview 1.3 External Specifications Page Overview 1.5 M3A-HS60 Block Diagram SH7206 CPU Board M3A-HS60 Overview 1.6 M3A-HS60 Board Overview Rev.1.00 June 1,2005 1-6 REJ11J0002-0100Z 1.6 M3A-HS60 Board Overview Figure1.6.1 shows the M3A-HS60 board overview. Page Overview 1.7 M3A-HS60 Memory Mapping Overview 1.8 Absolute Maximum Ratings 1.9 Recommended Operating Conditions Page Page Functional Overview 2.1 Functional Overview Functional Overview 2.2 CPU SH7206 Rev.1.00 June 1,2005 2-3 REJ11J0002-0100Z 2.2 CPU Functional Overview 2.3 Memory 2.3.1 SH7206's Internal RAM 2.3.2 Flash Memory M5M29KT331AVP (included as standard equipment) Page 2.3.3 External SDRAM Page 2.3.3 External SDRAM Rev.1.00 June 1,2005 2-8 REJ11J0002-0100Z Figure2.3.4 Typical SDRAM Single Read/Write Timing Functional Overview 2.4 Serial Port Interface Functional Overview 2.5 I/O Ports Page Functional Overview 2.6 Power Supply Circuit Functional Overview 2.7 Clock Module Functional Overview 2.8 Reset Module * * ) 2.9 Interrupt Switches Functional Overview 2.10 E10A-USB Rev.1.00 June 1,2005 2-15 REJ11J0002-0100Z 2.10 E10A-USB Interface Figure2.10.1 Block Diagram of the E10A-USB Interface Page Page Operational Specifications 3.1 M3A-HS60 Connectors Outline 3.1.1 H-UDI Connector (J1) 3.1.2 Serial Port Connector (J2) 3.1.3 External Power Supply Connectors(J3 and J5) 3.1.4 Power Supply Connector (J4) 3.1.5 User I/O Connectors (J6-J8) Page 3.1.6 Extension Connectors (J9-J13) Page Page Page Operational Specifications 3.2 Outline of Switches and LEDs 3.2.1 Power Supply Select Jumpers (JP1 and JP2) 3.2.2 Switch and LED Functions NMI RST MRES Page Operational Specifications 3.3 Outline Dimensions of M3A-HS60 Page Page Page SH-2A SH7206 CPU BOARD M3A-HS60 SCHEMATICS INDEX CPU SH7206 FLASH SDRAM UDI/RESET/UART/POWER BUS CONNECTORS/PUSH SW OTHERS [Note] :not mounted PAGE 1 2 3 4 5 6 7 TITLE SH7206 MD2 pin is fixed to "H" MD0 pin is fixed to "L" _CS0 = 16bit SH7206 Extention Connector 16bit Bus For SH7206 Bus Connector CLK 16.66MHz FLASH CSC CHANNEL 0 16bit access = 4MB Decoupling Caps SDRAM_SZ = "L" 16bit MODE DUMPING REGISTER for SDRAM SDRAM_SZ = "H" 32bit MODE EDS1216AATA EDS1216AATA User Port 1.2V EXTERNAL Mode Switch 5V TO 1.25V STEP DOWN REGULATOR SERIAL CONNECTOR(COM) Extension Bus Connector MRES MRES SWITCH CIRCUIT Extension Connector NMI UNUSED LOGIC AGND-GND TEST PIN