Renesas M3A-HS49, SH7149 - page 39

Operational Specifications

3.1.6 Extension Connectors (J9-J13)

Rev.1.0 Dec 15, 2006 3-13

REJ10J0917-0100

3

Table3.1.11 lists pin assignments of extension connectors (J12, J13).

Table3.1.11 Pin Assignments of Extension Connectors (J12, J13)

Pin

J13

Pin

J12 Signal Name Other connection

1 -

+5V -

2 -

+5V -

3 -

PA9/WA IT

_________/TCLKD/TXD2 -

4 -

NC -

5 -

NC -

6 -

NC -

7 -

NC -

8 -

NC -

9 -

NC -

10 -

NC -

11 -

NC -

12 -

NC -

13 -

NC -

14 -

NC -

15 -

NC -

16 -

NC -

17 -

NC -

18 -

NC -

19 -

NC -

20 -

GND -

21 1 NC -

22 2 NC -

23 3 PA 6/RD

_____/UBCTRG

_______________/TCLKA/POE4

_________ -

24 4 PD15/D15/AUDSYNC

________________ H-UDI Connector(J1)

25 5 PD14/D14/AUDCK H-UDI Connector(J1)

26 6 PD13/D13/AUDMD -

27 7 PD12/D12/AUDRST

______________ -

28 8 NC (PD11/D11/AUDATA3 when R55 mounted) H-UDI Connector(J1) when R55 mounted

29 9 NC (PD10/D10/AUDATA2 when R56 mounted) H-UDI Connector(J1) when R56 mounted

30 10 NC (PD9/D9/AUDATA1 when R57 mounted) H-UDI Connector(J1) when R57 mounted

31 11 NC (PD8/D8/SCK2/AUDATA0 when R58 mounted) H-UDI Connector(J1) when R58 mounted

32 12 PD7/D7/IRQ3/TXD2 User I/O Connector(J7)

33 13 PD6/D6/IRQ2/RXD2 User I/O Connector(J7)

34 14 PD5/D5/IRQ1/SCK1 User I/O Connector(J7)

35 15 PD4/D4/IRQ0/TXD1 -

36 16 PD3/D3/RXD1 -

37 17 PD2/D2/SCK0 -

38 18 PD1/D1/TXD0 -

39 19 PD0/D0/RXD0 -

40 20 GND -

Contents

Main REJ10J0917-0100 Rev. 1.0 Issued : Dec 15, 2006 PRELIMINARY M3 A -HS49 SH7149 CPU Board User's Manual Page Page Table of Contents Page Overview 1.1 Overview 1.2 Configuration Page Page Overview 1.5 M3A-HS49 Block Diagram SH7149 (80MHz) SH7149 CPU Board M3A-HS49 Overview 1.6 M3A-HS49 Board Overview * Rev.1.0 Dec 15, 2006 1-6 REJ10J0917-0100 1.6 M3A-HS49 Board Overview Page Overview 1.7 M3A-HS49 Memory Mapping Logical space of the SH7149 MCU mode 3 (Single Chip mode) Memory Mapping of the M3A-HS49 1.7 M3A-HS49 Memory Mapping Logical space of the SH7149 MCU mode 0,1 (On-chip ROM disabled mode) Memory Mapping of the M3A-HS49 Figure1.7.2 Memory Mapping Example of SH7149 (MCU mode 0,1) 1.7 M3A-HS49 Memory Mapping Rev.1.0 Dec 15, 2006 1-10 REJ10J0917-0100 Logical space of the SH7149 MCU mode 2 (On-chip ROM enabled mode) Memory Mapping of the M3A-HS49 Figure1.7.3 Memory Mapping Example of SH7149 (MCU mode 2) Overview 1.8 Absolute Maximum Ratings 1.9 Recommended Operating Conditions Page Page Page Functional Overview 2.2 CPU Rev.1.0 Dec 15, 2006 2-3 REJ10J0917-0100 2.2 CPU SH7149 Functional Overview 2.3 Serial Port Interface Functional Overview 2.4 I/O Ports SH7149 Page Functional Overview 2.5 Clock Module Output from a oscillator connected to EXTAL of the SH7149 Functional Overview 2.6 Reset Module Functional Overview 2.7 Interrupt Switches SH7149 Functional Overview 2.8 E10A-USB Interface Rev.1.0 Dec 15, 2006 2-10 REJ10J0917-0100 2.8 E10A-USB Interface Page Operational Specifications 3.1 M3A-HS49 Connectors Outline 3.1.1 H-UDI Connector (J1, J2) J2 3.1.2 Serial Port Connector (J3) 3.1.3 External Power Supply Connectors (J4) 3.1.4 Power Supply Connector (J5) 3.1.5 User I/O Connector (J6-J8) Page 3.1.6 Extension Connectors (J9-J13) Page Page Page 3.1.7 Extension Connector (J14) Operational Specifications 3.2 Outline of Switches and LEDs 3.2.1 SH7149 Power Supply Select Jumper (JP1) 3.2.2 FWE Pin Select Jumper (JP2) 3.2.3 Serial Port Select Jumpers (JP3,JP4) 3.2.4 Switch and LED Functions Page Page Page Page Page SH7149 CPU BOARD M3A-HS49 SCHEMATICS INDEX CPU SH7149 UDI/RESET/UART/POWER BUS CONNECTORS/PUSH SW OTHERS : not mounted[Note] PAGE 1 2 3 4 5 TITLE SH7149 10.00MHz CERALOCK Decoupling Caps 10.00MHz A/D User Port User Port Cd OFF OFF Mode 7S08 Extension Connector IRQ SWITCH CIRCUIT NMI NMI SWITCH CIRCUIT IRQ AGND-GND TEST PIN