Renesas M3A-HS49, SH7149 3.2.2 FWE Pin Select Jumper (JP2)

Operational Specifications

3.2.2 FWE Pin Select Jumper (JP2)

Rev.1.0 Dec 15, 2006 3-17

REJ10J0917-0100

3.2.2 FWE Pin Select Jumper (JP2)

The JP2 allows the connection for the FWE pin to be selected.

Figure3.2.2 shows the FWE pin select jumper (JP2) assignment.

Table3.2.1 lists the jumper setting for selecting FWE pin (JP2).

Top view of the

component side

Board

edge

Board

edge

JP2 FWESEL

Figure3.2.3 FWE Pin Select Jumper (JP2) Assignment

Table3.2.2 Jumper Setting for Selecting FWE pin (JP2)

Jumper Setting Function

1 - 2 The FWE pin of SH7149 is connected with DIP Switch (SW4-1). JP2

FWESEL 2 - 3 The FWE pin of SH7149 is connected with Extension Connector (J14).

: Initial Setting

Note : Do not change jumper settings while the operation of M3A-HS49. Ensure to turn off the power for the

M3A-HS49 before changing jumper settings.

Contents

Main REJ10J0917-0100 Rev. 1.0 Issued : Dec 15, 2006 PRELIMINARY M3 A -HS49 SH7149 CPU Board User's Manual Page Page Table of Contents Page Overview 1.1 Overview 1.2 Configuration Page Page Overview 1.5 M3A-HS49 Block Diagram SH7149 (80MHz) SH7149 CPU Board M3A-HS49 Overview 1.6 M3A-HS49 Board Overview * Rev.1.0 Dec 15, 2006 1-6 REJ10J0917-0100 1.6 M3A-HS49 Board Overview Page Overview 1.7 M3A-HS49 Memory Mapping Logical space of the SH7149 MCU mode 3 (Single Chip mode) Memory Mapping of the M3A-HS49 1.7 M3A-HS49 Memory Mapping Logical space of the SH7149 MCU mode 0,1 (On-chip ROM disabled mode) Memory Mapping of the M3A-HS49 Figure1.7.2 Memory Mapping Example of SH7149 (MCU mode 0,1) 1.7 M3A-HS49 Memory Mapping Rev.1.0 Dec 15, 2006 1-10 REJ10J0917-0100 Logical space of the SH7149 MCU mode 2 (On-chip ROM enabled mode) Memory Mapping of the M3A-HS49 Figure1.7.3 Memory Mapping Example of SH7149 (MCU mode 2) Overview 1.8 Absolute Maximum Ratings 1.9 Recommended Operating Conditions Page Page Page Functional Overview 2.2 CPU Rev.1.0 Dec 15, 2006 2-3 REJ10J0917-0100 2.2 CPU SH7149 Functional Overview 2.3 Serial Port Interface Functional Overview 2.4 I/O Ports SH7149 Page Functional Overview 2.5 Clock Module Output from a oscillator connected to EXTAL of the SH7149 Functional Overview 2.6 Reset Module Functional Overview 2.7 Interrupt Switches SH7149 Functional Overview 2.8 E10A-USB Interface Rev.1.0 Dec 15, 2006 2-10 REJ10J0917-0100 2.8 E10A-USB Interface Page Operational Specifications 3.1 M3A-HS49 Connectors Outline 3.1.1 H-UDI Connector (J1, J2) J2 3.1.2 Serial Port Connector (J3) 3.1.3 External Power Supply Connectors (J4) 3.1.4 Power Supply Connector (J5) 3.1.5 User I/O Connector (J6-J8) Page 3.1.6 Extension Connectors (J9-J13) Page Page Page 3.1.7 Extension Connector (J14) Operational Specifications 3.2 Outline of Switches and LEDs 3.2.1 SH7149 Power Supply Select Jumper (JP1) 3.2.2 FWE Pin Select Jumper (JP2) 3.2.3 Serial Port Select Jumpers (JP3,JP4) 3.2.4 Switch and LED Functions Page Page Page Page Page SH7149 CPU BOARD M3A-HS49 SCHEMATICS INDEX CPU SH7149 UDI/RESET/UART/POWER BUS CONNECTORS/PUSH SW OTHERS : not mounted[Note] PAGE 1 2 3 4 5 TITLE SH7149 10.00MHz CERALOCK Decoupling Caps 10.00MHz A/D User Port User Port Cd OFF OFF Mode 7S08 Extension Connector IRQ SWITCH CIRCUIT NMI NMI SWITCH CIRCUIT IRQ AGND-GND TEST PIN