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8. Cache Operation during User Program Break
When cache is enabled, the emulator accesses the memory by the following methods:
• At memory write: Writes through the cache, then writes to the memory.
• At memory read: Does not change the cache write mode that has been set.
Therefore, when memory read or write is performed during user program break, the cache state
will be changed.
9. Port G
The AUD and H-UDI pins are multiplexed as shown in table 2.2.
Table 2.2 Multiplexed Functions
Port Function 1 Function 2
G PTG5 input/output (port) *1/ASEBRKAK (H-UDI)
G PTG4 input/output (port) *2/AUDSYNC (AUD)
G PTG3 input/output (port) *2AUDATA3 (AUD)
G PTG2 input/output (port) *2AUDATA2 (AUD)
G PTG1 input/output (port) *2AUDATA1 (AUD)
G PTG0 input/output (port) *2AUDATA0 (AUD)
Notes: 1. PTG5 cannot be used when the emulator is used.
2. Function 1 can be used when the AUD pins of the device are not connected to the
emulator.
10.UBC
When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the
UBC can be used in the user program.
Do not use the UBC in the user program as it is used by the emulator when [EML] is specified
in the [UBC mode] list box in the [Configuration] dialog box.
11.MFI Boot Mode
When the MFI boot mode is used, be sure to allocate the boot program from the top of
MFRAM.
12.Using RWDT
At power-on reset, the operation of RWDT is enabled. When RWDT is not used, be sure to
disable the operation of RWDT at the top of the user-reset program.