Rev. 4.00 Sep. 14, 2005 Page xxii of l
18.7.13 Buffer Operation Setting in Complementary PWM Mode................................... 636
18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag.................. 637
18.7.15 Overflow Flags in Reset Sync PWM Mode..........................................................638
18.7.16 Conflict between Overflow/Underflow and Counter Clearing............................. 638
18.7.17 Conflict between TCNT Write and Overflow/Underflow.................................... 639
18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronous PWM Mode...........................................................................640
18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous
PWM Mode.......................................................................................................... 640
18.7.20 Interrupts in Module Standby Mode..................................................................... 640
18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in
Cascade Connection..............................................................................................640
18.8 MTU Output Pin Initialization...........................................................................................641
18.8.1 Operating Modes.................................................................................................. 641
18.8.2 Reset Start Operation............................................................................................ 641
18.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc.................. 642
18.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, Etc.................................................................................. 643
18.9 Port Output Enable (POE)................................................................................................. 673
18.9.1 Features.................................................................................................................673
18.9.2 Pin Configuration..................................................................................................675
18.9.3 Register Configuration..........................................................................................675
18.9.4 Operation.............................................................................................................. 681
Section 19 Serial Communication Interface with FIFO (SCIF)........................685
19.1 Overview............................................................................................................................685
19.1.1 Features.................................................................................................................685
19.2 Pin Configuration...............................................................................................................688
19.3 Register Description.......................................................................................................... 689
19.3.1 Receive Shift Register (SCRSR).......................................................................... 690
19.3.2 Receive FIFO Data Register (SCFRDR).............................................................. 690
19.3.3 Transmit Shift Register (SCTSR)......................................................................... 690
19.3.4 Transmit FIFO Data Register (SCFTDR).............................................................691
19.3.5 Serial Mode Register (SCSMR)............................................................................691
19.3.6 Serial Control Register (SCSCR)..........................................................................695
19.3.7 Serial Status Register (SCFSR)............................................................................ 699
19.3.8 Bit Rate Register (SCBRR).................................................................................. 707
19.3.9 FIFO Control Register (SCFCR).......................................................................... 714
19.3.10 FIFO Data Count Register (SCFDR).................................................................... 717
19.3.11 Serial Port Register (SCSPTR)............................................................................. 717