Rev. 5.00, 09/03, page 315 of 760
I/O Card Interface Timing: Figures 10.37 and 10.38 show the timing for the PCMCIA I/O card
interface.
Switching between the I/O card interface and the IC memory card interface is performed
according to the a cce sse d address . When PCMCIA is desi gned for physical space area 5, the bus
access is automatically performed as an I/O card interface access when a physical address from
H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6,
the bus access is automatically performed as an I/O card interface access when a physical address
from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area
in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width i s set f or are
5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is
recognized as being 8 bits in width. In this case, a data access fo r only 8 bits is per form ed in the
I/O b us cycle being executed, follo wed auto matically by a data access for the remaining 8 bi ts.
Figure 10.39 shows the basic timing for dynamic bus sizing.
In big-endi an m ode, th e IOIS16 s ignal is not supported, and should be fixed low.