Rev. 5.00, 09/03, page 360 of 760
CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
DREQ
Bus cycle
Bus returned to CPU
Read Write WriteRead
Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode
• Burst Mode
Once the bus is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In exte rnal request mode with low l evel detect ion of the DREQ pin,
howe ver, when the DREQ pin is driv en hi gh, the bus pas ses to the othe r bus m ast er after the
DMAC transfer request that has already been accepted ends, even if the transfer end conditions
have no t bee n satis fie d.
Burst mode cannot be used when a serial communication interface (IrDA, SCI), or A/D
converter is the transfer re qu est sou rce . Fi gure 11.1 3 shows an example of b urst mo de timing.
CPU CPU CPU DMAC DMAC DMAC DMACDMAC DMAC CPU
DREQ
Bus cycle
Read Read ReadWrite Write Write
Figure 11.13 Example of Transfer in Burst Mode