Rev. 5.00, 09/03, page 365 of 760
CKIO
DRAK
DREQ
DACK
Bus cycle DMAC(R)
CPU
DMAC(W)
DMAC(R)
CPU DMAC(W)
1st sampling 2nd sampling 3rd sampling
Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)