SanDisk CompactFlash Card OEM Product Manual ATA Command Description
Word 53: Translation Parameters Valid. Bit 0 of this field is set, indicating that words 54 to
58 are valid and reflect the current number of cylinders, heads and sectors. Bit 1 is also set,
indicating values in words 64 through 70 are valid.
Words 54-56: Current Number of Cylinders, Heads, Sectors/Track. These fields contain
the current number of user addressable cylinders, heads, and sectors/track in the current
translation mode.
Words 57-58: Current Capacity . This field contains the product of the current cylinders x
heads x sectors.
Word 59: Multiple Sector Setting . This field contains a validity flag in the odd byte and the
current number of sectors that can be transferred per interrupt for R/W Multiple in the even
byte. The odd byte is always 01H, which indicates that the even byte is always valid.
The even byte value depends on the value set by the Set Multiple command. The even byte of
this word by default contains a 00H, which indicates that R/W Multiple commands are not
valid. The only other value returned by the CompactFlash Memory Card in the even byte is a
01H value, which indicates that 1 sector per interrupt, can be transferred in R/W Multiple
mode.
Words 60-61: Total Sectors Addressable in LBA Mode. This field contains the number of
sectors addressable for the CompactFlash Card in LBA mode only.
Word 64: Advanced PIO Transfer Modes Supported. Bits 0 and 1 of this field are set to
indicate support for PIO transfer modes 3 and 4, respectively.
Word 65: Minimum Multiword DMA Transfer Cycle Time per Word. Word 65 of the
parameter information of the IDENTIFY DEVICE command is defined as the Minimum
Multiword DMA Transfer Cycle Time Per Word. This field defines, in nanoseconds, the
minimum cycle time that the device can support when performing Multiword DMA transfers
on a per word basis.
Word 66: Recommended Multiword DMA Cycle Time. Word 66 of the parameter
information of the IDENTIFY DEVICE command is defined as the Recommended Multiword
DMA Transfer Cycle Time. This field defines, in nanoseconds, the minimum cycle time per
word during a single sector host transfer while performing a multiple sector READ DMA or
WRITE DMA commands over all locations on the media under minimal conditions. If a host
runs at a faster cycle rate by operating at a cycle time of less that this value, the device may
negate DMARQ for flow control. The rate at which DMARQ is negated could result in
reduced throughput despite the faster cycled rate. Transfer at this rate does not ensure that flow
control will not be used, but implies that higher performance may result.
Word 67: Minimum PIO Transfer Cycle Time Without Flow Control. This field indicates
in nanoseconds, the minimum cycle time that, if used by the host, the card guarantees data
integrity during the cycle without utilization of flow control.
© 2007 SanDisk Corporation 5-9 Rev. 12.0, 02/07