Contents
2. Software Setup
CP2112 EVALUATION KIT USER ’S GUIDE 1. Kit Contents
Figure 1. Hardware Setup
3. CP2112 Hardware Interface
Figure 2. Configuration Tab
CP2112-EK
4. CP2112 Windows Application
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Figure 3. Data Transfer Tab
7. To Read data from an SMBus device non-addressed mode
8. To read data from an EEPROM or similar device addressed mode
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Figure 4. Pin Configuration Tab
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Figure 5. Customization Tab
5. Target Board
Pins
5.1. LED Headers J1, J2, J3, J4
Table 1. J2 and J3 LED Locations
5.4. VDD and VIO Power Connector J6
5.3. SMBus Signals TB1, H1
5.5. SMBus Pull-Up Voltage Connector J7
5.6. SUSPEND LED Connector J8
6. Schematic
Figure 7. CP2112 Evaluation Board Schematic
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision
CP2112-EK
CP2112-EK
CONTACT INFORMATION
Silicon Laboratories Inc 400 West Cesar Chavez Austin, TX Tel 1+512
Fax 1+512 Toll Free 1+877
