Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
Block Diagram
CLK32
CLOCKI
SER_IRQ
PCI_CLK
LAD[3:0]
LFrame#
LDRQ#
PCI_RESET#
IO_PME_S3*
IO_PME_S5*
IO_SMI*
GP1[0:4]*, GP21*,GP22*
GP27*, GP32*,GP33* GP36*, GP37* , GP4[0,2,3]* GP5[0:1]*, GP6[0:1]*
nMTR0, nTRK0, InNDEX nWGATE, nHDSEL DRVDEN0*, nWRTPRT
nDIR, nSTEP nDSKCHG, nDS0,
nRDATA, nWDATA
SDA1
SCLK1
SDA2
SCLK2
WDT*
CLOCK |
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GEN |
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SERIAL |
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IRQ |
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LPC |
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Bus Interface |
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Power Mgmt |
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General |
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Purpose |
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I/O |
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| 32 byte |
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SMSC |
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| Security |
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Proprietary |
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82077 |
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Compatible |
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Floppydisk |
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| PCI RESET# |
Controller with |
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| HWN INT | 14.318Mhz |
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Digital Data |
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| SLP S3# | SLP S5# | 96 Mhz | |||
Separator & |
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Write Precom- |
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pensation |
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SMbus | M |
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Isola- | B |
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tion |
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Switch | u |
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| INT VREF | PECI |
| IN IN IN IN - | - | Out PWM2 EN# | SEL | |||
LED1* |
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LEDs
Parallel Port
with
ChiProtectTM/
FDC MUX
(see LPC47B27x)
16550A
UART
PORT 1
16550A
UART
PORT 2
PCI Reset
Outputs
Keyboard/Mouse
8042
controller
Power Control and Recovery
Intruder
Detection
PD[7,0]
BUSY, SLCT, PE, nERROR, nACK
nSTROBE, nINIT, nSLCTIN, nALF
TXD1*, RXD1
nCTS1, nRTS1*
nDSR1, nDTR1 nDCD1, nRI1
TXD2 (IRTX)*,
RXD2 (IRRX)*
CTS2*, RTS2 *
DSR2*, DTR2*
DCD2*, RI2*
nIDE_RSTDRV*
nPCIRST_OUT[1:4]*
MCLK*, MDAT*
A20M*
nKBDRST* KCLK*, KDAT*
nFPRST, PB_IN#
PWRGD_PS
`SLP_S3#, SLP_S5# PWRGD_CPU , PWRGD_3V SLP_S3DEL#
PS_ON# nRSMRST
nINTRD_IN
SDA SCLK | nHWM_ | PECI REQUEST#* | READY VID3/PWMA VID4/PWMB VID5 / FANTACH3 V1 V2 VCCP +2.5VTR Remote1 Remote1+ Remote2 Remote2+ PWM1/xTest | PWM3/ ADDR_ FANTACH1 FANTACH2 FANTACH4/ ADDR_ PWMA*, PWMB* FANTACHA* FANTACHB* |
Note 1: This diagram does not show power and ground connections.
Note 2: Signal names followed by an asterisk (*) are located on multifunction pins. This diagram is designed to show the various functions available on the chip and should not be used as a pin layout .
Figure 1 SCH5027E Block Diagram
Revision 0.2 | PRODUCT4 PREVIEW | SMSC SCH5027E |