Datasheet
Table 5.4 SMBus Slave Interface Register Map (continued)
REG | R/W | REGISTER NAME | ABBR | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
ADDR | (MSB) | (LSB) | |||||||||
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0Ch | R/W | Max Power (Self) | MAXPS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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0Dh | R/W | Max Power (Bus) | MAXPB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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0Eh | R/W | Hub Controller | HCMCS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| Max Current (Self) |
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0Fh | R/W | Hub Controller | HCMCB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| Max Current (bus) |
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10h | R/W | PWRT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
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BIT |
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NUMBER | BIT NAME |
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7:3 | Reserved | Reserved. {Note: Software must never write a ‘1’ to these bits} | |
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2 | RESET | Reset the SMBus Interface and internal memory back to RESET_N assertion | |
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| default settings. {Note: During this reset, this bit is automatically cleared to | |
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| its default value of 0.} | |
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| 0 | = Normal Run/Idle State. |
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| 1 | = Force a reset. |
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1 | WRITE_PROT | Write Protect: The external SMBus host sets this bit after the Hub’s internal | |
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| memory is loaded with configuration data. {Note: The External SMBus Host | |
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| is responsible for verification of downloaded data.} | |
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| 0 | = The internal memory (address range |
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| 1 | = The internal memory (address range |
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| prevent unintentional data corruption.} | |
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| {Note: This bit is write once and is only cleared by assertion of the external | |
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| RESET_N pin.} | |
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0 | USB_ATTACH | USB Attach & | |
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| 0 | = Default; SMBus slave interface is active. |
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| 1 = Hub will signal a USB attach event to an upstream device, Note: SMBus | |
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| Slave interface will completely power down after the ACK has completed. | |
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| {Note: This bit is write once and is only cleared by assertion of the external | |
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| RESET_N pin.} | |
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NUMBER | BIT NAME | DESCRIPTION |
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7:0 | VID_LSB | Least Significant Byte of the Vendor ID. |
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SMSC USB2502 | 27 | Revision 2.3 |
| DATASHEET |
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