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| Integrated USB 2.0 Compatible |
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| Datasheet |
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| Table 4.3 Miscellaneous Pins (continued) | ||
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NAME | SYMBOL |
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Crystal Output | XTAL2 |
| OCLKx | 24MHz Crystal |
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| This is the other terminal of the crystal, or left |
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| unconnected when an external clock source is used to |
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| drive XTAL1/CLKIN. It must not be used to drive any |
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| external circuitry other than the crystal circuit. |
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Clock Input | CLKIN_EN |
| I | Clock In Enable: |
Enable |
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| Low = XTAL1 and XTAL2 pins configured for use with |
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| external crystal |
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| High = XTAL1 pin configured as CLKIN, and must be |
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| driven by an external CMOS clock. |
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RESET Input | RESET_N |
| IS | This active low signal is used by the system to reset the |
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| chip. The minimum active low pulse is 100ns. |
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SELF_PWR |
| I | Detects availability of local | |
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| Low = Self/local power source is NOT available (i.e., 7- | |
Detect |
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| Port Hub gets all power from Upstream USB VBus). |
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| High = Self/local power source is available. |
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TEST Pins | TEST[1:0] |
| IPD | Used for testing the chip. User must treat as a no- |
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| connect or connect to ground. For board testing, all |
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| signal pins are included in an XNOR chain, Please see |
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| Chapter 6, "XNOR Test," on page 37 for more details on |
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| the configuration and use of the XNOR mode. |
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Analog Test | ATEST/ |
| AIO | This signal is used for testing the analog section of the |
& | REG_EN |
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| chip, and to enable or disable the internal 1.8v regulator. |
Internal 1.8V |
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| This pin must be connected to VDDA3P3 to enable the |
voltage |
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| internal 1.8V regulator, or to VSS to disable the internal | |
regulator |
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| regulator. | |
enable |
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| When the internal regulator is enabled, the 1.8V power |
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| pins must be left unconnected, except for the required |
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| bypass capacitors.When the PHY is in test mode, the |
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| internal regulator is disabled and the ATEST pin |
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| functions as a test pin. |
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| Table 4.4 Power, Ground, and No Connect | ||
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NAME | SYMBOL |
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VDD1P8 | VDD18 |
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| +1.8V core power. |
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| If the internal regulator is enabled, then VDD18 pin |
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| closest to VDD33CR must have a 4.7μF (or greater) |
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| ±20% (ESR <0.1Ω) capacitor to VSS |
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VDDPLL1P8 | VDDA18PLL |
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| +1.8V Filtered analog power for internal PLL. |
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| If the internal regulator is enabled, then this pin must |
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| have a 4.7μF (or greater) ±20% (ESR <0.1Ω) capacitor |
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| to VSS |
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VDDAPLL3P3 | VDDA33PLL |
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| +3.3V Filtered analog power for the internal PLL |
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| If the internal PLL 1.8V regulator is enabled, then this pin |
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| acts as the regulator input |
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VDDA3P3 | VDDA33 |
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| +3.3V Filtered analog power. |
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Revision 2.3 | 12 | SMSC USB2503/USB2503A |
| DATASHEET |
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