Integrated USB 2.0 Compatible
Datasheet
Table 4.3 Miscellaneous Pins (continued)
NAME | SYMBOL | TYPE | FUNCTION |
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Analog Test | ATEST/ | AIO | This signal is used for testing the analog section of the |
& | REG_EN |
| chip, and to enable or disable the internal 1.8v regulator. |
Internal 1.8V |
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| This pin must be connected to VDDA33 to enable the |
voltage |
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| internal 1.8V regulator, or to VSS to disable the internal | |
regulator |
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| regulator. | |
enable |
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| When the internal regulator is enabled, the 1.8V power |
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| pins must be left unconnected, except for the required |
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| bypass capacitors.When the PHY is in test mode, the |
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| internal regulator is disabled and the ATEST pin |
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| functions as a test pin. |
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Table 4.4 Power, Ground, and No Connect
NAME | SYMBOL | TYPE | FUNCTION |
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VDDCORE3P3 | VDD33CR |
| +3.3V I/O Power. |
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| If the internal core 1.8V regulator is enabled, then this pin |
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| acts as the regulator input |
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VDD1P8 | VDD18 |
| +1.8V core power. |
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| If the internal regulator is enabled, then VDD18 pin 50 |
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| must have a 4.7μF (or greater) ±20% (ESR <0.1Ω) |
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| capacitor to VSS |
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VDDAPLL3P3 | VDDA33PLL |
| +3.3V Filtered analog power for the internal PLL |
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| If the internal PLL 1.8V regulator is enabled, then this pin |
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| acts as the regulator input |
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VDDAPLL1P8 | VDDA18PLL |
| +1.8V Filtered analog power for internal PLL. |
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| If the internal regulator is enabled, then this pin must |
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| have a 4.7μF (or greater) ±20% (ESR <0.1Ω) capacitor |
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| to VSS |
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VDDIO3P3 | VDD33 |
| +3.3V I/O power. |
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VDDA3P3 | VDDA33 |
| +3.3V Filtered analog power. |
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VSS | VSS |
| Ground. |
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| Table 4.5 Buffer Type Descriptions | |
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BUFFER |
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| DESCRIPTION |
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I | Input. |
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IPD | Input, with a weak Internal | ||
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IPU | Input, with a weak Internal |
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IS | Input with Schmitt trigger. |
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O12 | Output 12mA. |
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SMSC USB2507 | 13 | Revision 2.3 |
| DATASHEET |
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