Industrial Temperature Rated USB 2.0
Datasheet
Table 3.2 SMBus or EEPROM Interface Behavior (continued)CFG_SEL1 |
| CFG_SEL0 |
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| SMBUS OR EEPROM INTERFACE BEHAVIOR | |
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0 |
| 1 |
| Configured as an SMBus slave for external download of | ||
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| descriptors. | |
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| | SMBus slave address 58 (0101100x) |
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| | Strap Options Disabled |
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| | All Settings Controlled by Registers |
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1 |
| 0 |
| Internal Default Configuration | ||
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| | Strap Options Enabled |
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| | Bus Power Operation |
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1 |
| 1 |
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| | Strap Options Disabled |
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| | All Settings Controlled by Registers |
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| Table 3.3 USB2512i Power, Ground, and No Connect | |||
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| PACKAGE SYMBOL |
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| FUNCTION | |||
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VDD18 |
| 14 |
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| VDD Core | |
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| This pin must have a 1.0μF (or greater) ±20% (ESR <0.1Ω) capacitor to |
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| VSS. |
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VDD33PLL |
| 36 |
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| VDD 3.3 PLL Regulator Reference | |
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| +3.3V power supply for the PLL. If the internal PLL 1.8V regulator |
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| is enabled, then this pin acts as the regulator input. |
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VDDPLL18 |
| 34 |
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| VDD PLL | |
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| This pin must have a 1.0μF (or greater) ±20% (ESR <0.1Ω) capacitor to |
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| VSS. |
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VDDA33 |
| 5 |
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| VDD Analog I/O | |
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| 10 |
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| +3.3V Filtered analog PHY power, shared between adjacent ports. |
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| 29 |
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VDD33/VDD33CR |
| 23 |
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| VDDIO/VDD 3.3 Core Regulator Reference | |
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| 15 |
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| +3.3V power supply for the Digital I/O |
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| If the internal core regulator is enabled, then VDD33CR acts as the |
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| regulator input. |
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NC |
| 6 |
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| No Connect | |
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| 7 |
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| Leave unconnected on the circuit board. |
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| 8 |
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| 9 |
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| 18 |
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| 19 |
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| 20 |
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| 21 |
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SMSC USB2512i | 11 | Revision 1.92 |
| DATASHEET |
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