SMSC USB3310 PRODUCT5 PREVIEW, Table 1 USB3310 Pin Description (continued), VDD3.3, DATA[7], DATA[6], DATA[5, DATA[4], CLKOUT, DATA[3], DATA[2], REFSEL[1], REFSEL[0], NXT

Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock

Table 1 USB3310 Pin Description (continued)

PIN		DIRECTION/	ACTIVE
BALL	NAME	TYPE	LEVEL			DESCRIPTION
4	VDD3.3	Power	N/A	3.3V Regulator Output. A 2.2uF (<1 ohm
D2				ESR) bypass capacitor to ground is
				required for regulator stability. The
				bypass capacitor should be placed as
				close as possible to the USB3310.
5	DM	I/O,	N/A	D- pin of the USB cable.
D1		Analog
6	DP	I/O,	N/A	D+ pin of the USB cable.
E1		Analog
7	DATA[7]	I/O,	N/A	ULPI bi-directional data bus. DATA[7] is
E2		CMOS		the MSB.
8	DATA[6]	I/O,	N/A	ULPI bi-directional data bus.
E3		CMOS
9	DATA[5	I/O,	N/A	ULPI bi-directional data bus.
D3		CMOS
10	DATA[4]	I/O,	N/A	ULPI bi-directional data bus.
E4		CMOS
11	CLKOUT	Output,	N/A	60MHz reference clock output. All ULPI
E5		CMOS		signals are driven synchronous to the
				rising edge of this clock.
12	DATA[3]	I/O,	N/A	ULPI bi-directional data bus.
D5		CMOS
13	DATA[2]	I/O,	N/A	ULPI bi-directional data bus.
D4		CMOS
14	REFSEL[1]	Input,	N/A	These signals select one of the available
C4		CMOS		reference frequencies:
				[1]	[0]	Description
				0	0	13MHz
15	REFSEL[0]	Input,	N/A
				0	1	19.2MHz
B4		CMOS		1	0	26MHz
				1	1	24MHz
16	DATA[1]	I/O,	N/A	ULPI bi-directional data bus.
C5		CMOS
17	DATA[0]	I/O,	N/A	ULPI bi-directional data bus. DATA[0] is
B5		CMOS		the LSB.
18	NXT	Output,	High	The PHY asserts NXT to throttle the data.
A5		CMOS		When the Link is sending data to the
				PHY, NXT indicates when the current
				byte has been accepted by the PHY. The
				Link places the next byte on the data bus
				in the following clock cycle.

SMSC USB3310 REV C PRODUCT5 PREVIEW Revision 1.11 (10-31-08)