Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock

Table 1 USB3310 Pin Description (continued)

PIN

 

DIRECTION/

ACTIVE

 

BALL

NAME

TYPE

LEVEL

DESCRIPTION

 

 

 

 

 

19

DIR

Output,

N/A

Controls the direction of the data bus.

A4

 

CMOS

 

When the PHY has data to transfer to the

 

 

 

Link, it drives DIR high to take ownership

 

 

 

 

 

 

 

 

of the bus. When the PHY has no data to

 

 

 

 

transfer it drives DIR low and monitors

 

 

 

 

the bus for commands from the Link.

 

 

 

 

 

20

STP

Input,

High

The Link asserts STP for one clock cycle

A3

 

CMOS

 

to stop the data stream currently on the

 

 

 

bus. If the Link is sending data to the

 

 

 

 

 

 

 

 

PHY, STP indicates the last byte of data

 

 

 

 

was on the bus in the previous cycle.

 

 

 

 

 

21

VDD1.8

Power

N/A

External 1.8V Supply input pin. This pad

B3

 

 

 

needs to be bypassed with a 0.1uF

 

 

 

capacitor to ground, placed as close as

 

 

 

 

 

 

 

 

possible to the USB3310.

 

 

 

 

 

22

RESETB

Input,

N/A

When low, the part is suspended with all

B2

 

CMOS,

 

of the I/O tri-stated. When high the

 

 

 

USB3310 will operate as a normal ULPI

 

 

 

 

 

 

 

 

device.

 

 

 

 

 

23

REFCLK

Input,

N/A

Reference Clock input.The required

A2

 

CMOS

 

frequency is configured by the

 

 

 

REFSEL[1:0] pins.

 

 

 

 

 

 

 

 

 

24

RBIAS

Analog,

N/A

Rbias pin. This pin requires an 8.06kΩ

A1

 

CMOS

 

(±1%) resistor to ground, placed as close

 

 

 

as possible to the USB3310.

 

 

 

 

 

 

 

 

 

FLAG
GND

Ground

N/A

Ground.

C3

 

 

 

QFN only: The flag should be connected

 

 

 

to the ground plane with a via array

 

 

 

 

 

 

 

 

under the exposed flag. This is the main

 

 

 

 

ground for the IC.

 

 

 

 

 

Revision 1.11 (10-31-08)

PRODUCT6 PREVIEW

SMSC USB3310 REV C